From: Sean Paul Date: Wed, 10 Sep 2014 14:52:05 +0000 (-0400) Subject: gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=b298e98ef6ab9c4279b427db717a1624ef722751;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register During calibration, sets the "internal reference level for drive pull- down" to the value specified in the Tegra TRM. Signed-off-by: Sean Paul Signed-off-by: Thierry Reding --- diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c index 22e20c2399c5..fbc6ee6ca337 100644 --- a/drivers/gpu/host1x/mipi.c +++ b/drivers/gpu/host1x/mipi.c @@ -72,6 +72,7 @@ #define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0) #define MIPI_CAL_BIAS_PAD_CFG1 0x17 +#define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16) #define MIPI_CAL_BIAS_PAD_CFG2 0x18 #define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1) @@ -203,6 +204,9 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device) value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF; tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0); + tegra_mipi_writel(device->mipi, MIPI_CAL_BIAS_PAD_DRV_DN_REF(2), + MIPI_CAL_BIAS_PAD_CFG1); + value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2); value &= ~MIPI_CAL_BIAS_PAD_PDVREG; tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);