From: Florian Fainelli <florian@openwrt.org>
Date: Tue, 14 Jan 2014 17:54:40 +0000 (-0800)
Subject: MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=af2418be63b4e994cfe4b625939d65b9afdfdf6c;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git

MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value

Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
value of 4) instead of the currently configured 32 bytes L1-cache line
size.

Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
---

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index db8fae3341e2..9a05292cfae7 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -138,6 +138,7 @@ config BCM63XX
 	select SWAP_IO_SPACE
 	select ARCH_REQUIRE_GPIOLIB
 	select HAVE_CLK
+	select MIPS_L1_CACHE_SHIFT_4
 	help
 	 Support for BCM63XX based boards