From: Ville Syrjälä Date: Tue, 15 Mar 2016 14:40:05 +0000 (+0200) Subject: drm/i915: Fix CHV DSI PLL refclk during state readout X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=ae9ec62bdadc4cd3bf893d6baced80aa3a5dbbd6;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git drm/i915: Fix CHV DSI PLL refclk during state readout Use the proper refclock frequency (100MHz) when reading out the current DSI clock on CHV. Signed-off-by: Ville Syrjälä Link: http://patchwork.freedesktop.org/patch/msgid/1458052809-23426-13-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index bd17465018f4..7ad59d13dd4c 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -258,7 +258,7 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) u32 dsi_clock, pclk; u32 pll_ctl, pll_div; u32 m = 0, p = 0, n; - int refclk = 25000; + int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; int i; DRM_DEBUG_KMS("\n");