From: Slava Grigorev <slava.grigorev@amd.com>
Date: Wed, 23 Mar 2016 03:34:29 +0000 (-0400)
Subject: drm/amd/amdgpu: fix 64-bit division
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=ae17c999f0a679aa71577e1a0f488c680aae316c;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

drm/amd/amdgpu: fix 64-bit division

Signed-off-by: Slava Grigorev <slava.grigorev@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6be83f183f16..aeb9caee5c1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -942,14 +942,14 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 		goto out;
 	}
 
-	tmp = (unsigned int *)((uint64_t)rlc_hdr +
+	tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 			le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 	for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
 		adev->gfx.rlc.register_list_format[i] =	le32_to_cpu(tmp[i]);
 
 	adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 
-	tmp = (unsigned int *)((uint64_t)rlc_hdr +
+	tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 			le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 	for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
 		adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 715bc3d56924..a5172d154da5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -23,6 +23,7 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/fb.h>
+#include <asm/div64.h>
 #include "linux/delay.h"
 #include "pp_acpi.h"
 #include "hwmgr.h"
@@ -981,7 +982,8 @@ static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 	sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 	temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 	temp <<= 0x10;
-	sclk_setting->Fcw_frac = (uint16_t)(0xFFFF & (temp / ref_clock));
+	do_div(temp, ref_clock);
+	sclk_setting->Fcw_frac = temp & 0xffff;
 
 	pcc_target_percent = 10; /*  Hardcode 10% for now. */
 	pcc_target_freq = clock - (clock * pcc_target_percent / 100);
@@ -995,7 +997,8 @@ static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 		sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 		temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 		temp <<= 0x10;
-		sclk_setting->Fcw1_frac = (uint16_t)(0xFFFF & (temp / ref_clock));
+		do_div(temp, ref_clock);
+		sclk_setting->Fcw1_frac = temp & 0xffff;
 	}
 
 	return 0;