From: John Crispin Date: Mon, 4 Jan 2016 19:23:57 +0000 (+0100) Subject: MIPS: ralink: fix USB frequency scaling X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=ad310161f513b4ad8cf82eb4fc3de990e9412270;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git MIPS: ralink: fix USB frequency scaling commit fad2522272ed5ed451d2d7b1dc547ddf3781cc7e upstream. Commit 418d29c87061 ("MIPS: ralink: Unify SoC id handling") was not fully correct. The logic for the SoC check got inverted. We need to check if it is not a MT76x8. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11992/ Signed-off-by: Ralf Baechle Signed-off-by: Amit Pundir Signed-off-by: Greg Kroah-Hartman --- diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 733768e9877c..4c17dc6e8ae9 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -459,7 +459,7 @@ void __init ralink_clk_init(void) ralink_clk_add("10000c00.uartlite", periph_rate); ralink_clk_add("10180000.wmac", xtal_rate); - if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) { + if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) { /* * When the CPU goes into sleep mode, the BUS clock will be * too low for USB to function properly. Adjust the busses