From: Maciej W. Rozycki Date: Thu, 15 Jun 2017 23:06:19 +0000 (+0100) Subject: MIPS: Actually decode JALX in `__compute_return_epc_for_insn' X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=a9db101b735a9d49295326ae41f610f6da62b08c;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git MIPS: Actually decode JALX in `__compute_return_epc_for_insn' Complement commit fb6883e5809c ("MIPS: microMIPS: Support handling of delay slots.") and actually decode the regular MIPS JALX major instruction opcode, the handling of which has been added with the said commit for EPC calculation in `__compute_return_epc_for_insn'. Fixes: fb6883e5809c ("MIPS: microMIPS: Support handling of delay slots.") Signed-off-by: Maciej W. Rozycki Cc: James Hogan Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # 3.9+ Patchwork: https://patchwork.linux-mips.org/patch/16394/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c index f702a459a830..40cc3def36a4 100644 --- a/arch/mips/kernel/branch.c +++ b/arch/mips/kernel/branch.c @@ -556,6 +556,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, /* * These are unconditional and in j_format. */ + case jalx_op: case jal_op: regs->regs[31] = regs->cp0_epc + 8; case j_op: