From: Damien Lespiau <damien.lespiau@intel.com>
Date: Wed, 11 Feb 2015 18:21:44 +0000 (+0000)
Subject: drm/i915/skl: Use a LRI for WaDisableDgMirrorFixInHalfSliceChicken5
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=a86eb582e3863daa00f6f60355d7fb91252d0e43;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

drm/i915/skl: Use a LRI for WaDisableDgMirrorFixInHalfSliceChicken5

I have no idea how that crept in, but we need to do the write from the
ring and this is a masked register. Two fixes in 1!

Cc: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ab8ce4ceed2e..e758c0592675 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -959,13 +959,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 
 	if (INTEL_REVID(dev) == SKL_REVID_A0 ||
 	    INTEL_REVID(dev) == SKL_REVID_B0) {
-		/*
-		* WaDisableDgMirrorFixInHalfSliceChicken5:skl
-		* This is a pre-production w/a.
-		*/
-		I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
-			I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
-			~GEN9_DG_MIRROR_FIX_ENABLE);
+		/* WaDisableDgMirrorFixInHalfSliceChicken5:skl */
+		WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
+				  GEN9_DG_MIRROR_FIX_ENABLE);
 	}
 
 	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {