From: Janghyuck Kim <janghyuck.kim@samsung.com>
Date: Mon, 21 Aug 2017 02:33:25 +0000 (+0900)
Subject: [COMMON] media: scaler: add reset sequence for scaler 5.0.1
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=a860b70cb769a1dcd79f41bbda27e6261ee35a1b;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

[COMMON] media: scaler: add reset sequence for scaler 5.0.1

Change-Id: Iedfb4b3a0ac1b544ad62e2da062c4cab547f00b1
Signed-off-by: Janghyuck Kim <janghyuck.kim@samsung.com>
---

diff --git a/drivers/media/platform/exynos/scaler/scaler-core.c b/drivers/media/platform/exynos/scaler/scaler-core.c
index eed4b15850c5..8c76f5fab1e9 100644
--- a/drivers/media/platform/exynos/scaler/scaler-core.c
+++ b/drivers/media/platform/exynos/scaler/scaler-core.c
@@ -330,7 +330,7 @@ static const struct sc_fmt sc_formats[] = {
 
 /* must specify in revers order of SCALER_VERSION(xyz) */
 static const u32 sc_version_table[][2] = {
-	{ 0x02000100, SCALER_VERSION(5, 0, 0) }, /* SC_POLY */
+	{ 0x02000100, SCALER_VERSION(5, 0, 1) }, /* SC_POLY */
 	{ 0x02000000, SCALER_VERSION(5, 0, 0) },
 	{ 0x80060007, SCALER_VERSION(4, 2, 0) }, /* SC_BI */
 	{ 0x0100000f, SCALER_VERSION(4, 0, 1) }, /* SC_POLY */
@@ -350,6 +350,30 @@ static const u32 sc_version_table[][2] = {
 
 static const struct sc_variant sc_variant[] = {
 	{
+		.limit_input = {
+			.min_w		= 16,
+			.min_h		= 16,
+			.max_w		= 8192,
+			.max_h		= 8192,
+		},
+		.limit_output = {
+			.min_w		= 4,
+			.min_h		= 4,
+			.max_w		= 8192,
+			.max_h		= 8192,
+		},
+		.version		= SCALER_VERSION(5, 0, 1),
+		.sc_up_max		= SCALE_RATIO_CONST(1, 8),
+		.sc_down_min		= SCALE_RATIO_CONST(4, 1),
+		.sc_up_swmax		= SCALE_RATIO_CONST(1, 64),
+		.sc_down_swmin		= SCALE_RATIO_CONST(16, 1),
+		.blending		= 0,
+		.prescale		= 0,
+		.ratio_20bit		= 1,
+		.initphase		= 1,
+		.pixfmt_10bit		= 1,
+		.extra_buf		= 1,
+	}, {
 		.limit_input = {
 			.min_w		= 16,
 			.min_h		= 16,
@@ -2610,6 +2634,7 @@ static int sc_run_next_job(struct sc_dev *sc)
 	d_frame = &ctx->d_frame;
 
 	sc_hwset_init(sc);
+	sc_hwset_clk_request(sc, true);
 
 	if (ctx->i_frame) {
 		set_bit(CTX_INT_FRAME, &ctx->flags);
@@ -2780,6 +2805,8 @@ static irqreturn_t sc_irq_handler(int irq, void *priv)
 	if (!SCALER_INT_OK(irq_status))
 		sc_hwset_soft_reset(sc);
 
+	sc_hwset_clk_request(sc, false);
+
 	clear_bit(DEV_RUN, &sc->state);
 	clear_bit(CTX_RUN, &ctx->flags);
 
diff --git a/drivers/media/platform/exynos/scaler/scaler-regs.h b/drivers/media/platform/exynos/scaler/scaler-regs.h
index daf6faa261df..c305a6dc0060 100644
--- a/drivers/media/platform/exynos/scaler/scaler-regs.h
+++ b/drivers/media/platform/exynos/scaler/scaler-regs.h
@@ -29,6 +29,8 @@
 #define SCALER_CFG_BURST_WR		(1 << 8)
 #define SCALER_CFG_BURST_RD		(1 << 7)
 #define SCALER_CFG_CSC_Y_OFFSET_DST	(1 << 9)
+#define SCALER_CFG_STOP_REQ		(1 << 3)
+#define SCALER_CFG_RESET_OKAY		(1 << 2)
 #define SCALER_CFG_SOFT_RST		(1 << 1)
 #define SCALER_CFG_START_CMD		(1 << 0)
 
@@ -176,6 +178,7 @@
 
 #define SCALER_TIMEOUT_CTRL		0x2c0
 #define SCALER_TIMEOUT_CNT		0x2c4
+#define SCALER_CLK_REQ			0x2cc
 
 #define SCALER_SRC_YH_INIT_PHASE	0x2d0
 #define SCALER_SRC_YV_INIT_PHASE	0x2d4
@@ -187,6 +190,12 @@
 #define SCALER_VAL_SRC_POS(l, t) (((l) & 0x3FFF) << 18) | (((t) & 0x3FFF) << 2)
 #define SCALER_VAL_DST_POS(l, t) (((l) & 0x3FFF) << 16) | ((t) & 0x3FFF)
 
+static inline void sc_hwset_clk_request(struct sc_dev *sc, bool enable)
+{
+	if (sc->version == SCALER_VERSION(5, 0, 1))
+		__raw_writel(enable ? 1 : 0, sc->regs + SCALER_CLK_REQ);
+}
+
 static inline void sc_hwset_src_pos(struct sc_dev *sc, __s32 left, __s32 top,
 				unsigned int chshift, unsigned int cvshift)
 {
@@ -273,6 +282,19 @@ static inline void sc_hwset_init(struct sc_dev *sc)
 {
 	unsigned long cfg;
 
+	if (sc->version == SCALER_VERSION(5, 0, 1)) {
+		int cnt = 1000;
+
+		__raw_writel(SCALER_CFG_STOP_REQ, sc->regs + SCALER_CFG);
+
+		while (cnt-- > 0)
+			if (__raw_readl(sc->regs + SCALER_CFG)
+						& SCALER_CFG_RESET_OKAY)
+				break;
+
+		WARN_ON(cnt <= 0);
+	}
+
 #ifdef SC_NO_SOFTRST
 	cfg = (SCALER_CFG_CSC_Y_OFFSET_SRC | SCALER_CFG_CSC_Y_OFFSET_DST);
 #else