From: Helge Deller Date: Sat, 29 Jun 2013 11:24:16 +0000 (+0200) Subject: parisc: document the shadow registers X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=a83f58bcb24003b9de2364de7c829a263423ead7;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git parisc: document the shadow registers Signed-off-by: Helge Deller Cc: # 3.10 --- diff --git a/Documentation/parisc/registers b/Documentation/parisc/registers index dd3caddd1ad9..10c7d1730f5d 100644 --- a/Documentation/parisc/registers +++ b/Documentation/parisc/registers @@ -77,6 +77,14 @@ PSW default E value 0 Shadow Registers used by interruption handler code TOC enable bit 1 +========================================================================= + +The PA-RISC architecture defines 7 registers as "shadow registers". +Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce +the state save and restore time by eliminating the need for general register +(GR) saves and restores in interruption handlers. +Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25. + ========================================================================= Register usage notes, originally from John Marvin, with some additional notes from Randolph Chung.