From: Philipp Zabel Date: Fri, 28 Jun 2013 12:24:15 +0000 (+0200) Subject: ARM i.MX6DL: parent LDB DI clocks to PLL5 on i.MX6S/DL X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=a6fc9d194d9abc2a8abc85866912810228f0653f;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git ARM i.MX6DL: parent LDB DI clocks to PLL5 on i.MX6S/DL i.MX6S/DL have the Video PLL post dividers fixed already in revision 1.0 Signed-off-by: Philipp Zabel Signed-off-by: Shawn Guo --- diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 86567d980b07..82a85cea7ce0 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -554,7 +554,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); - if (imx6q_revision() != IMX_CHIP_REVISION_1_0) { + if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); }