From: David S. Miller Date: Thu, 10 Nov 2016 02:20:01 +0000 (-0500) Subject: Merge branch 'PHC-freq-fine-tuning' X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=a6dfdb4e1cd8ea0cf3e8588b97a0c33f8ad3fa4b;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git Merge branch 'PHC-freq-fine-tuning' Richard Cochran says: ==================== PHC frequency fine tuning This series expands the PTP Hardware Clock subsystem by adding a method that passes the frequency tuning word to the the drivers without dropping the low order bits. Keeping those bits is useful for drivers whose frequency resolution is higher than 1 ppb. The appended script (below) runs a simple demonstration of the improvement. This test needs two Intel i210 PCIe cards installed in the same PC, with their SDP0 pins connected by copper wire. Measuring the estimated offset (from the ptp4l servo) and the true offset (from the PPS) over one hour yields the following statistics. | | Est. Before | Est. After | True Before | True After | |--------+---------------+---------------+---------------+---------------| | min | -5.200000e+01 | -1.600000e+01 | -3.100000e+01 | -1.000000e+00 | | max | +5.700000e+01 | +2.500000e+01 | +8.500000e+01 | +4.000000e+01 | | pk-pk: | +1.090000e+02 | +4.100000e+01 | +1.160000e+02 | +4.100000e+01 | | mean | +6.472222e-02 | +1.277778e-02 | +2.422083e+01 | +1.826083e+01 | | stddev | +1.158006e+01 | +4.581982e+00 | +1.207708e+01 | +4.981435e+00 | Here the numbers in units of nanoseconds, and the ~20 nanosecond PPS offset is due to input/output delays on the i210's external interface logic. With the series applied, both the peak to peak error and the standard deviation improve by a factor of more than two. These two graphs show the improvement nicely. http://linuxptp.sourceforge.net/fine-tuning/fine-est.png http://linuxptp.sourceforge.net/fine-tuning/fine-tru.png ==================== Signed-off-by: David S. Miller --- a6dfdb4e1cd8ea0cf3e8588b97a0c33f8ad3fa4b