From: Anton Blanchard <anton@samba.org>
Date: Tue, 6 Sep 2005 04:52:12 +0000 (+1000)
Subject: [PATCH] ppc64: Use num_pmcs in oprofile code
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=a6908cd00036080fbea14ff67335e5f2a1ab5489;p=GitHub%2Fmt8127%2Fandroid_kernel_alcatel_ttab.git

[PATCH] ppc64: Use num_pmcs in oprofile code

Change oprofile to use num_pmcs from the cpu feature struct.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
---

diff --git a/arch/ppc64/oprofile/common.c b/arch/ppc64/oprofile/common.c
index 4acd1a424933..a376eb2a1f0f 100644
--- a/arch/ppc64/oprofile/common.c
+++ b/arch/ppc64/oprofile/common.c
@@ -16,6 +16,7 @@
 #include <asm/ptrace.h>
 #include <asm/system.h>
 #include <asm/pmc.h>
+#include <asm/cputable.h>
 
 #include "op_impl.h"
 
@@ -131,7 +132,6 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
 		case PV_630:
 		case PV_630p:
 			model = &op_model_rs64;
-			model->num_counters = 8;
 			ops->cpu_type = "ppc64/power3";
 			break;
 
@@ -140,14 +140,12 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
 		case PV_ICESTAR:
 		case PV_SSTAR:
 			model = &op_model_rs64;
-			model->num_counters = 8;
 			ops->cpu_type = "ppc64/rs64";
 			break;
 
 		case PV_POWER4:
 		case PV_POWER4p:
 			model = &op_model_power4;
-			model->num_counters = 8;
 			ops->cpu_type = "ppc64/power4";
 			break;
 
@@ -155,14 +153,12 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
 		case PV_970FX:
 		case PV_970MP:
 			model = &op_model_power4;
-			model->num_counters = 8;
 			ops->cpu_type = "ppc64/970";
 			break;
 
 		case PV_POWER5:
 		case PV_POWER5p:
 			model = &op_model_power4;
-			model->num_counters = 6;
 			ops->cpu_type = "ppc64/power5";
 			break;
 
@@ -170,6 +166,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
 			return -ENODEV;
 	}
 
+	model->num_counters = cur_cpu_spec->num_pmcs;
 	ops->create_files = op_ppc64_create_files;
 	ops->setup = op_ppc64_setup;
 	ops->shutdown = op_ppc64_shutdown;
diff --git a/arch/ppc64/oprofile/op_model_power4.c b/arch/ppc64/oprofile/op_model_power4.c
index 3d103d66870d..e469610efde5 100644
--- a/arch/ppc64/oprofile/op_model_power4.c
+++ b/arch/ppc64/oprofile/op_model_power4.c
@@ -23,7 +23,6 @@
 
 static unsigned long reset_value[OP_MAX_COUNTER];
 
-static int num_counters;
 static int oprofile_running;
 static int mmcra_has_sihv;
 
@@ -45,8 +44,6 @@ static void power4_reg_setup(struct op_counter_config *ctr,
 {
 	int i;
 
-	num_counters = num_ctrs;
-
 	/*
 	 * SIHV / SIPR bits are only implemented on POWER4+ (GQ) and above.
 	 * However we disable it on all POWER4 until we verify it works
@@ -68,7 +65,7 @@ static void power4_reg_setup(struct op_counter_config *ctr,
 
 	backtrace_spinlocks = sys->backtrace_spinlocks;
 
-	for (i = 0; i < num_counters; ++i)
+	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
 		reset_value[i] = 0x80000000UL - ctr[i].count;
 
 	/* setup user and kernel profiling */
@@ -121,7 +118,7 @@ static void power4_start(struct op_counter_config *ctr)
 	/* set the PMM bit (see comment below) */
 	mtmsrd(mfmsr() | MSR_PMM);
 
-	for (i = 0; i < num_counters; ++i) {
+	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
 		if (ctr[i].enabled) {
 			ctr_write(i, reset_value[i]);
 		} else {
@@ -272,7 +269,7 @@ static void power4_handle_interrupt(struct pt_regs *regs,
 	/* set the PMM bit (see comment below) */
 	mtmsrd(mfmsr() | MSR_PMM);
 
-	for (i = 0; i < num_counters; ++i) {
+	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
 		val = ctr_read(i);
 		if (val < 0) {
 			if (oprofile_running && ctr[i].enabled) {