From: Hideo Saito <saito@densan.co.jp>
Date: Thu, 14 Feb 2008 05:45:08 +0000 (+0900)
Subject: sh: Fix multiple UTLB hit on UP SH-4.
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=a602cc05f8fc849023e72e2857bd842f0104f648;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

sh: Fix multiple UTLB hit on UP SH-4.

This acts as a reversion of 1c6b2ca5e0939bf8b5d1a11f1646f25189ecd447 in
the case of UP SH-4, where we still have the risk of a multiple hit
between the slow and fast paths. As seen on SH7780.

Signed-off-by: Hideo Saito <saito@densan.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
---

diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c
index 4ef0a1f1a9ab..d1fa27594c6e 100644
--- a/arch/sh/mm/fault_32.c
+++ b/arch/sh/mm/fault_32.c
@@ -299,6 +299,14 @@ asmlinkage int __kprobes __do_page_fault(struct pt_regs *regs,
 		entry = pte_mkdirty(entry);
 	entry = pte_mkyoung(entry);
 
+#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SMP)
+	/*
+	 * ITLB is not affected by "ldtlb" instruction.
+	 * So, we need to flush the entry by ourselves.
+	 */
+	local_flush_tlb_one(get_asid(), address & PAGE_MASK);
+#endif
+
 	set_pte(pte, entry);
 	update_mmu_cache(NULL, address, entry);