From: Thierry Reding Date: Thu, 5 Jun 2014 14:16:23 +0000 (+0200) Subject: drm/tegra: sor - Do not hardcode link speed X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=a4263fed284282665c24ca1f3335bddde3a76d57;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git drm/tegra: sor - Do not hardcode link speed Use the speed probed from the link at runtime rather than relying on a hardcoded default. Signed-off-by: Thierry Reding --- diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index ff025aa786e8..4e354ee4b203 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -658,10 +658,10 @@ static int tegra_output_sor_enable(struct tegra_output *output) usleep_range(250, 1000); } - /* set link bandwidth (2.7 GHz, XXX: parameterize based on link?) */ + /* set link bandwidth */ value = tegra_sor_readl(sor, SOR_CLK_CNTRL); value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; - value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; + value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; tegra_sor_writel(sor, value, SOR_CLK_CNTRL); /* set linkctl */