From: Weiguang Ruan Date: Thu, 3 Aug 2017 11:35:15 +0000 (+0800) Subject: wifi: add pci wifi ap6356p [1/3] X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=a2ec4ae5088008428df12985e9406b9cab32f50b;p=GitHub%2FLineageOS%2FG12%2Fandroid_hardware_amlogic_kernel-modules_dhd-driver.git wifi: add pci wifi ap6356p [1/3] PD# 148564 bsaed version: bcmdhd.1.363.59.144.x.cn Change-Id: I4eaecfe479e413f43b5b11a36f92854adfbf5596 Signed-off-by: Weiguang Ruan --- diff --git a/bcmdhd.1.363.59.144.x.cn/Makefile b/bcmdhd.1.363.59.144.x.cn/Makefile index 28d199b..d8b7686 100644 --- a/bcmdhd.1.363.59.144.x.cn/Makefile +++ b/bcmdhd.1.363.59.144.x.cn/Makefile @@ -2,10 +2,13 @@ # 1. WL_IFACE_COMB_NUM_CHANNELS must be added if Android version is 4.4 with Kernel version 3.0~3.4, # otherwise please remove it. +# if not confiure pci mode, we use sdio mode as default +ifeq ($(CONFIG_BCMDHD_PCIE),) +$(info bcm SDIO driver configured) CONFIG_BCMDHD_SDIO := y -#CONFIG_BCMDHD_PCIE := y -CONFIG_BCMDHD_PROPTXSTATUS := y CONFIG_DHD_USE_STATIC_BUF :=y +endif +CONFIG_BCMDHD_PROPTXSTATUS := y export CONFIG_BCMDHD = m export CONFIG_BCMDHD_OOB = y @@ -62,6 +65,8 @@ endif ifneq ($(CONFIG_BCMDHD_PCIE),) DHDCFLAGS += \ -DPCIE_FULL_DONGLE -DBCMPCIE -DCUSTOM_DPC_PRIO_SETTING=-1 +DHDCFLAGS += -DDHD_PCIE_BAR1_WIN_BASE_FIX=0x200000 +DHDCFLAGS += -DDHD_USE_MSI DHDOFILES += dhd_pcie.o dhd_pcie_linux.o pcie_core.o dhd_flowring.o \ dhd_msgbuf.o diff --git a/bcmdhd.1.363.59.144.x.cn/dhd_pcie.c b/bcmdhd.1.363.59.144.x.cn/dhd_pcie.c index d6fc50d..fb29fd8 100644 --- a/bcmdhd.1.363.59.144.x.cn/dhd_pcie.c +++ b/bcmdhd.1.363.59.144.x.cn/dhd_pcie.c @@ -118,6 +118,10 @@ static uint32 dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset); static void dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data); static uint64 dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset); static void dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data); +#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX) +static void dhdpcie_bus_cfg_set_bar1_win(dhd_bus_t *bus, uint32 data); +static ulong dhd_bus_cmn_check_offset(dhd_bus_t *bus, ulong offset); +#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */ static void dhdpcie_bus_reg_unmap(osl_t *osh, ulong addr, int size); static int dhdpcie_cc_nvmshadow(dhd_bus_t *bus, struct bcmstrbuf *b); static void dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data); @@ -301,8 +305,13 @@ dhdpcie_bus_reg_unmap(osl_t *osh, ulong addr, int size) * * 'tcm' is the *host* virtual address at which tcm is mapped. */ +#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX) +dhd_bus_t* dhdpcie_bus_attach(osl_t *osh, + volatile char *regs, volatile char *tcm, uint32 tcm_size, void *pci_dev) +#else dhd_bus_t* dhdpcie_bus_attach(osl_t *osh, volatile char *regs, volatile char *tcm, void *pci_dev) +#endif /* DHD_PCIE_BAR1_WIN_BASE_FIX */ { dhd_bus_t *bus; @@ -316,6 +325,9 @@ dhd_bus_t* dhdpcie_bus_attach(osl_t *osh, bus->regs = regs; bus->tcm = tcm; +#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX) + bus->tcm_size = tcm_size; +#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */ bus->osh = osh; /* Save pci_dev into dhd_bus, as it may be needed in dhd_attach */ bus->dev = (struct pci_dev *)pci_dev; @@ -573,12 +585,18 @@ dhdpcie_dongle_attach(dhd_bus_t *bus) /* Set bar0 window to si_enum_base */ dhdpcie_bus_cfg_set_bar0_win(bus, SI_ENUM_BASE); +#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX) + /* Read bar1 window */ + bus->bar1_win_base = OSL_PCI_READ_CONFIG(bus->osh, PCI_BAR1_WIN, 4); + DHD_ERROR(("%s: PCI_BAR1_WIN = %x\n", __FUNCTION__, bus->bar1_win_base)); +#else /* Checking PCIe bus status with reading configuration space */ val = OSL_PCI_READ_CONFIG(osh, PCI_CFG_VID, sizeof(uint32)); if ((val & 0xFFFF) != VENDOR_BROADCOM) { DHD_ERROR(("%s : failed to read PCI configuration space!\n", __FUNCTION__)); goto fail; } +#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */ /* si_attach() will provide an SI handle and scan the backplane */ if (!(bus->sih = si_attach((uint)devid, osh, regsva, PCI_BUS, bus, @@ -594,6 +612,14 @@ dhdpcie_dongle_attach(dhd_bus_t *bus) /* WAR where the BAR1 window may not be sized properly */ W_REG(osh, &sbpcieregs->configaddr, 0x4e0); val = R_REG(osh, &sbpcieregs->configdata); +#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX) + /* Fix to 2M */ + val = 22; /* 1M: 21, 2M: 22, 4M: 23 */ + bus->bar1_win_mask = 0xffffffff - (bus->tcm_size - 1); + DHD_ERROR(("%s: BAR1 window val=%d, base=%d mask=%x, tcm=%x(%x)\n", __FUNCTION__, val, + bus->bar1_win_base, bus->bar1_win_mask, + bus->tcm_size, DHD_PCIE_BAR1_WIN_BASE_FIX)); +#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */ W_REG(osh, &sbpcieregs->configdata, val); /* Get info on the ARM and SOCRAM cores... */ @@ -941,6 +967,14 @@ dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data) OSL_PCI_WRITE_CONFIG(bus->osh, PCI_BAR0_WIN, 4, data); } +#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX) +static void +dhdpcie_bus_cfg_set_bar1_win(dhd_bus_t *bus, uint32 data) +{ + OSL_PCI_WRITE_CONFIG(bus->osh, PCI_BAR1_WIN, 4, data); +} +#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */ + void dhdpcie_bus_dongle_setmemsize(struct dhd_bus *bus, int mem_size) { @@ -2093,6 +2127,9 @@ dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uin uint dsize; int detect_endian_flag = 0x01; bool little_endian; +#if defined(CONFIG_64BIT) || defined(DHD_PCIE_BAR1_WIN_BASE_FIX) + bool is_64bit_unaligned; +#endif /* defined(CONFIG_64BIT) || defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */ if (write && bus->is_linkdown) { DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__)); @@ -2102,6 +2139,11 @@ dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uin /* Detect endianness. */ little_endian = *(char *)&detect_endian_flag; +#if defined(CONFIG_64BIT) || defined(DHD_PCIE_BAR1_WIN_BASE_FIX) + /* Check 64bit aligned or not. */ + is_64bit_unaligned = (address & 0x7); +#endif /* defined(CONFIG_64BIT) || defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */ + /* In remap mode, adjust address beyond socram and redirect * to devram at SOCDEVRAM_BP_ADDR since remap address > orig_ramsize * is not backplane accessible @@ -2111,15 +2153,22 @@ dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uin dsize = sizeof(uint64); /* Do the transfer(s) */ - DHD_INFO(("%s: %s %d bytes in window 0x%08lx\n", - __FUNCTION__, (write ? "write" : "read"), size, address)); if (write) { while (size) { - if (size >= sizeof(uint64) && little_endian && -#ifdef CONFIG_64BIT - !(address % 8) && -#endif /* CONFIG_64BIT */ - 1) { + if (size >= sizeof(uint64) && little_endian) { +#if defined(CONFIG_64BIT) || defined(DHD_PCIE_BAR1_WIN_BASE_FIX) + if (is_64bit_unaligned) { + DHD_INFO(("%s: write unaligned %lx\n", + __FUNCTION__, address)); + dhdpcie_bus_wtcm32(bus, address, *((uint32 *)data)); + data += 4; + size -= 4; + address += 4; + is_64bit_unaligned = (address & 0x7); + continue; + } + else +#endif dhdpcie_bus_wtcm64(bus, address, *((uint64 *)data)); } else { dsize = sizeof(uint8); @@ -2134,11 +2183,20 @@ dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uin } } else { while (size) { - if (size >= sizeof(uint64) && little_endian && -#ifdef CONFIG_64BIT - !(address % 8) && -#endif /* CONFIG_64BIT */ - 1) { + if (size >= sizeof(uint64) && little_endian) { +#if defined(CONFIG_64BIT) || defined(DHD_PCIE_BAR1_WIN_BASE_FIX) + if (is_64bit_unaligned) { + DHD_INFO(("%s: read unaligned %lx\n", + __FUNCTION__, address)); + *(uint32 *)data = dhdpcie_bus_rtcm32(bus, address); + data += 4; + size -= 4; + address += 4; + is_64bit_unaligned = (address & 0x7); + continue; + } + else +#endif *(uint64 *)data = dhdpcie_bus_rtcm64(bus, address); } else { dsize = sizeof(uint8); @@ -2403,11 +2461,32 @@ dhd_bus_rx_frame(struct dhd_bus *bus, void* pkt, int ifidx, uint pkt_count) dhd_rx_frame(bus->dhd, ifidx, pkt, pkt_count, 0); } +#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX) +static ulong dhd_bus_cmn_check_offset(dhd_bus_t *bus, ulong offset) +{ + uint new_bar1_wbase = 0; + ulong address = 0; + + new_bar1_wbase = (uint)offset & bus->bar1_win_mask; + if (bus->bar1_win_base != new_bar1_wbase) { + bus->bar1_win_base = new_bar1_wbase; + dhdpcie_bus_cfg_set_bar1_win(bus, bus->bar1_win_base); + DHD_ERROR(("%s: offset=%lx, switch bar1_win_base to %x\n", + __FUNCTION__, offset, bus->bar1_win_base)); + } + + address = offset - bus->bar1_win_base; + return address; +} +#else +#define dhd_bus_cmn_check_offset(x, y) y +#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */ + /** 'offset' is a backplane address */ void dhdpcie_bus_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data) { - *(volatile uint8 *)(bus->tcm + offset) = (uint8)data; + *(volatile uint8 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)) = (uint8)data; } uint8 @@ -2415,7 +2494,7 @@ dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset) { volatile uint8 data; - data = *(volatile uint8 *)(bus->tcm + offset); + data = *(volatile uint8 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)); return data; } @@ -2423,17 +2502,17 @@ dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset) void dhdpcie_bus_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data) { - *(volatile uint32 *)(bus->tcm + offset) = (uint32)data; + *(volatile uint32 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)) = (uint32)data; } void dhdpcie_bus_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data) { - *(volatile uint16 *)(bus->tcm + offset) = (uint16)data; + *(volatile uint16 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)) = (uint16)data; } void dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data) { - *(volatile uint64 *)(bus->tcm + offset) = (uint64)data; + *(volatile uint64 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)) = (uint64)data; } uint16 @@ -2441,7 +2520,7 @@ dhdpcie_bus_rtcm16(dhd_bus_t *bus, ulong offset) { volatile uint16 data; - data = *(volatile uint16 *)(bus->tcm + offset); + data = *(volatile uint16 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)); return data; } @@ -2451,7 +2530,7 @@ dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset) { volatile uint32 data; - data = *(volatile uint32 *)(bus->tcm + offset); + data = *(volatile uint32 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)); return data; } @@ -2461,7 +2540,7 @@ dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset) { volatile uint64 data; - data = *(volatile uint64 *)(bus->tcm + offset); + data = *(volatile uint64 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)); return data; } @@ -4210,14 +4289,14 @@ dhdpcie_bus_write_vars(dhd_bus_t *bus) bzero(vbuffer, varsize); bcopy(bus->vars, vbuffer, bus->varsz); /* Write the vars list */ - DHD_INFO_HW4(("%s: tcm: %p varaddr: 0x%x varsize: %d\n", + DHD_ERROR(("%s: tcm: %p varaddr: 0x%x varsize: %d\n", __FUNCTION__, bus->tcm, varaddr, varsize)); bcmerror = dhdpcie_bus_membytes(bus, TRUE, varaddr, vbuffer, varsize); /* Implement read back and verify later */ #ifdef DHD_DEBUG /* Verify NVRAM bytes */ - DHD_INFO(("%s: Compare NVRAM dl & ul; varsize=%d\n", __FUNCTION__, varsize)); + DHD_ERROR(("%s: Compare NVRAM dl & ul; varsize=%d\n", __FUNCTION__, varsize)); nvram_ularray = (uint8*)MALLOC(bus->dhd->osh, varsize); if (!nvram_ularray) return BCME_NOMEM; @@ -4250,9 +4329,9 @@ dhdpcie_bus_write_vars(dhd_bus_t *bus) phys_size += bus->dongle_ram_base; /* adjust to the user specified RAM */ - DHD_INFO(("%s: Physical memory size: %d, usable memory size: %d\n", __FUNCTION__, + DHD_ERROR(("%s: Physical memory size: %d, usable memory size: %d\n", __FUNCTION__, phys_size, bus->ramsize)); - DHD_INFO(("%s: Vars are at %d, orig varsize is %d\n", __FUNCTION__, + DHD_ERROR(("%s: Vars are at %d, orig varsize is %d\n", __FUNCTION__, varaddr, varsize)); varsize = ((phys_size - 4) - varaddr); diff --git a/bcmdhd.1.363.59.144.x.cn/dhd_pcie.h b/bcmdhd.1.363.59.144.x.cn/dhd_pcie.h index 511d00e..dc65947 100644 --- a/bcmdhd.1.363.59.144.x.cn/dhd_pcie.h +++ b/bcmdhd.1.363.59.144.x.cn/dhd_pcie.h @@ -73,7 +73,11 @@ extern int exynos_pcie_deregister_event(struct exynos_pcie_register_event *reg); #define PCMSGBUF_HDRLEN 0 #define DONGLE_REG_MAP_SIZE (32 * 1024) +#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX) +#define DONGLE_TCM_MAP_SIZE DHD_PCIE_BAR1_WIN_BASE_FIX +#else #define DONGLE_TCM_MAP_SIZE (4096 * 1024) +#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */ #define DONGLE_MIN_MEMSIZE (128 *1024) #ifdef DHD_DEBUG #define DHD_PCIE_SUCCESS 0 @@ -185,6 +189,11 @@ typedef struct dhd_bus { uint32 dma_rxoffset; volatile char *regs; /* pci device memory va */ volatile char *tcm; /* pci device memory va */ +#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX) + uint32 tcm_size; + uint32 bar1_win_base; + uint32 bar1_win_mask; +#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */ osl_t *osh; uint32 nvram_csm; /* Nvram checksum */ uint16 pollrate; @@ -254,8 +263,13 @@ extern int dhdpcie_bus_register(void); extern void dhdpcie_bus_unregister(void); extern bool dhdpcie_chipmatch(uint16 vendor, uint16 device); +#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX) +extern struct dhd_bus* dhdpcie_bus_attach(osl_t *osh, + volatile char *regs, volatile char *tcm, uint32 tcm_size, void *pci_dev); +#else extern struct dhd_bus* dhdpcie_bus_attach(osl_t *osh, volatile char *regs, volatile char *tcm, void *pci_dev); +#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */ extern uint32 dhdpcie_bus_cfg_read_dword(struct dhd_bus *bus, uint32 addr, uint32 size); extern void dhdpcie_bus_cfg_write_dword(struct dhd_bus *bus, uint32 addr, uint32 size, uint32 data); extern void dhdpcie_bus_intr_enable(struct dhd_bus *bus); diff --git a/bcmdhd.1.363.59.144.x.cn/dhd_pcie_linux.c b/bcmdhd.1.363.59.144.x.cn/dhd_pcie_linux.c index 0fef810..c1c054c 100644 --- a/bcmdhd.1.363.59.144.x.cn/dhd_pcie_linux.c +++ b/bcmdhd.1.363.59.144.x.cn/dhd_pcie_linux.c @@ -615,10 +615,16 @@ dhdpcie_request_irq(dhdpcie_info_t *dhdpcie_info) if (!bus->irq_registered) { snprintf(dhdpcie_info->pciname, sizeof(dhdpcie_info->pciname), "dhdpcie:%s", pci_name(pdev)); +#ifdef DHD_USE_MSI + pci_enable_msi(pdev); +#endif /* DHD_USE_MSI */ err = request_irq(pdev->irq, dhdpcie_isr, IRQF_SHARED, dhdpcie_info->pciname, bus); if (err) { DHD_ERROR(("%s: request_irq() failed\n", __FUNCTION__)); +#ifdef DHD_USE_MSI + pci_disable_msi(pdev); +#endif /* DHD_USE_MSI */ return -1; } else { bus->irq_registered = TRUE; @@ -710,9 +716,9 @@ int dhdpcie_get_resource(dhdpcie_info_t *dhdpcie_info) } #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */ - DHD_TRACE(("%s:Phys addr : reg space = %p base addr 0x"PRINTF_RESOURCE" \n", + DHD_ERROR(("%s:Phys addr : reg space = %p base addr 0x"PRINTF_RESOURCE" \n", __FUNCTION__, dhdpcie_info->regs, bar0_addr)); - DHD_TRACE(("%s:Phys addr : tcm_space = %p base addr 0x"PRINTF_RESOURCE" \n", + DHD_ERROR(("%s:Phys addr : tcm_space = %p base addr 0x"PRINTF_RESOURCE" \n", __FUNCTION__, dhdpcie_info->tcm, bar1_addr)); return 0; /* SUCCESS */ @@ -865,7 +871,11 @@ int dhdpcie_init(struct pci_dev *pdev) } /* Bus initialization */ +#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX) + bus = dhdpcie_bus_attach(osh, dhdpcie_info->regs, dhdpcie_info->tcm, dhdpcie_info->tcm_size, pdev); +#else bus = dhdpcie_bus_attach(osh, dhdpcie_info->regs, dhdpcie_info->tcm, pdev); +#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */ if (!bus) { DHD_ERROR(("%s:dhdpcie_bus_attach() failed\n", __FUNCTION__)); break; @@ -1005,6 +1015,9 @@ dhdpcie_free_irq(dhd_bus_t *bus) pdev = bus->dev; free_irq(pdev->irq, bus); bus->irq_registered = FALSE; +#ifdef DHD_USE_MSI + pci_disable_msi(pdev); +#endif /* DHD_USE_MSI */ } else { DHD_ERROR(("%s: PCIe IRQ is not registered\n", __FUNCTION__)); } @@ -1247,10 +1260,13 @@ dhdpcie_alloc_resource(dhd_bus_t *bus) } bus->tcm = dhdpcie_info->tcm; +#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX) + bus->tcm_size = dhdpcie_info->tcm_size; +#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */ - DHD_TRACE(("%s:Phys addr : reg space = %p base addr 0x"PRINTF_RESOURCE" \n", + DHD_ERROR(("%s:Phys addr : reg space = %p base addr 0x"PRINTF_RESOURCE" \n", __FUNCTION__, dhdpcie_info->regs, bar0_addr)); - DHD_TRACE(("%s:Phys addr : tcm_space = %p base addr 0x"PRINTF_RESOURCE" \n", + DHD_ERROR(("%s:Phys addr : tcm_space = %p base addr 0x"PRINTF_RESOURCE" \n", __FUNCTION__, dhdpcie_info->tcm, bar1_addr)); return 0; diff --git a/bcmdhd.1.363.59.144.x.cn/wl_cfg80211.c b/bcmdhd.1.363.59.144.x.cn/wl_cfg80211.c index f10029d..db1c77e 100644 --- a/bcmdhd.1.363.59.144.x.cn/wl_cfg80211.c +++ b/bcmdhd.1.363.59.144.x.cn/wl_cfg80211.c @@ -1490,9 +1490,9 @@ wl_cfg80211_add_virtual_iface(struct wiphy *wiphy, #ifdef PROP_TXSTATUS_VSDB #if defined(BCMSDIO) s32 up = 1; - dhd_pub_t *dhd; bool enabled; #endif + dhd_pub_t *dhd; #endif /* PROP_TXSTATUS_VSDB */ #if defined(SUPPORT_AP_POWERSAVE) dhd_pub_t *dhd; @@ -1502,11 +1502,7 @@ wl_cfg80211_add_virtual_iface(struct wiphy *wiphy, if (!cfg) return ERR_PTR(-EINVAL); -#ifdef PROP_TXSTATUS_VSDB -#if defined(BCMSDIO) dhd = (dhd_pub_t *)(cfg->pub); -#endif -#endif /* PROP_TXSTATUS_VSDB */ #if defined(SUPPORT_AP_POWERSAVE) dhd = (dhd_pub_t *)(cfg->pub); #endif /* SUPPORT_AP_POWERSAVE */