From: Mike Frysinger <vapier@gentoo.org>
Date: Mon, 27 Jun 2011 19:46:40 +0000 (-0400)
Subject: Blackfin: dpmc: optimize SDRAM programming slightly
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=9e770f77801fce713f5736c66f8441467eb36db5;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

Blackfin: dpmc: optimize SDRAM programming slightly

No need to reload these registers constantly since they're always
available (we're not making any function calls in between).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---

diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 2d1c3ce19fb1..1c534d298de4 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -196,21 +196,20 @@ ENTRY(_set_dram_srfs)
 #else 				/* SDRAM */
 	P0.L = lo(EBIU_SDGCTL);
 	P0.H = hi(EBIU_SDGCTL);
+	P1.L = lo(EBIU_SDSTAT);
+	P1.H = hi(EBIU_SDSTAT);
+
 	R2 = [P0];
 	BITSET(R2, 24); /* SRFS enter self-refresh mode */
 	[P0] = R2;
 	SSYNC;
 
-	P0.L = lo(EBIU_SDSTAT);
-	P0.H = hi(EBIU_SDSTAT);
 1:
-	R2 = w[P0];
+	R2 = w[P1];
 	SSYNC;
 	cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
 	if !cc jump 1b;
 
-	P0.L = lo(EBIU_SDGCTL);
-	P0.H = hi(EBIU_SDGCTL);
 	R2 = [P0];
 	BITCLR(R2, 0); /* SCTLE disable CLKOUT */
 	[P0] = R2;
@@ -220,6 +219,7 @@ ENDPROC(_set_dram_srfs)
 
 ENTRY(_unset_dram_srfs)
 	/*  set the dram out of self refresh mode */
+
 #if defined(EBIU_RSTCTL)	/* DDR */
 	P0.H = hi(EBIU_RSTCTL);
 	P0.L = lo(EBIU_RSTCTL);
@@ -227,20 +227,21 @@ ENTRY(_unset_dram_srfs)
 	BITCLR(R2, 3); /* clear SRREQ bit */
 	[P0] = R2;
 #elif defined(EBIU_SDGCTL)	/* SDRAM */
-
-	P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
+	/* release CLKOUT from self-refresh */
+	P0.L = lo(EBIU_SDGCTL);
 	P0.H = hi(EBIU_SDGCTL);
+
 	R2 = [P0];
 	BITSET(R2, 0); /* SCTLE enable CLKOUT */
 	[P0] = R2
 	SSYNC;
 
-	P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
-	P0.H = hi(EBIU_SDGCTL);
+	/* release SDRAM from self-refresh */
 	R2 = [P0];
 	BITCLR(R2, 24); /* clear SRFS bit */
 	[P0] = R2
 #endif
+
 	SSYNC;
 	RTS;
 ENDPROC(_unset_dram_srfs)