From: Arnd Bergmann Date: Sat, 29 Mar 2014 01:03:39 +0000 (+0100) Subject: Merge tag 'exynos-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene... X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=9e0c42ea3d2c8e24e6ad27a6d749b3085f1a2430;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git Merge tag 'exynos-cleanup' of git://git./linux/kernel/git/kgene/linux-samsung into next/cleanup3 Merge "Exynos cleanup for v3.15" from Kukjin Kim: - reorganize code for - add support reserve memory for mfc-v7 - consolidate exynos4 and exynos5 machine codes - add generic compatible strings for exynos4 and exynos5 - update DT with generic compatible strings - move clk related dt-binding header file in dt-bindings/clock * tag 'exynos-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock ARM: dts: Update Exynos DT files with generic compatible strings ARM: EXYNOS: Add generic compatible strings ARM: EXYNOS: Consolidate exynos4 and exynos5 machine files ARM: EXYNOS: Consolidate CPU init code ARM: SAMSUNG: Introduce generic Exynos4 and 5 helpers ARM: EXYNOS: Add support to reserve memory for MFC-v7 ARM: SAMSUNG: Reorganize calls to reserve memory for MFC Conflicts: arch/arm/mach-exynos/exynos.c Signed-off-by; Arnd Bergmann --- 9e0c42ea3d2c8e24e6ad27a6d749b3085f1a2430 diff --cc arch/arm/boot/dts/exynos4212.dtsi index ceefc711793c,34e578d15301..3c00e6ec9302 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@@ -20,13 -20,18 +20,13 @@@ #include "exynos4x12.dtsi" / { - compatible = "samsung,exynos4212"; + compatible = "samsung,exynos4212", "samsung,exynos4"; - gic: interrupt-controller@10490000 { - cpu-offset = <0x8000>; + combiner: interrupt-controller@10440000 { + samsung,combiner-nr = <18>; }; - interrupt-controller@10440000 { - samsung,combiner-nr = <18>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 107 0>, <0 108 0>; + gic: interrupt-controller@10490000 { + cpu-offset = <0x8000>; }; }; diff --cc arch/arm/boot/dts/exynos4412.dtsi index a40b6e20e92f,eaa67899ed31..15d3c0ac2f5f --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@@ -20,13 -20,19 +20,13 @@@ #include "exynos4x12.dtsi" / { - compatible = "samsung,exynos4412"; + compatible = "samsung,exynos4412", "samsung,exynos4"; - gic: interrupt-controller@10490000 { - cpu-offset = <0x4000>; - }; - - interrupt-controller@10440000 { + combiner: interrupt-controller@10440000 { samsung,combiner-nr = <20>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; }; + gic: interrupt-controller@10490000 { + cpu-offset = <0x4000>; + }; }; diff --cc arch/arm/mach-exynos/Makefile index 58fe9e6f542f,71df742fee25..a656dbe3b78c --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@@ -12,9 -12,9 +12,9 @@@ obj- : # Core - obj-$(CONFIG_ARCH_EXYNOS) += common.o + obj-$(CONFIG_ARCH_EXYNOS) += exynos.o -obj-$(CONFIG_S5P_PM) += pm.o +obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --cc arch/arm/mach-exynos/exynos.c index 000000000000,fd3664f7244a..4987ec7711c3 mode 000000,100644..100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@@ -1,0 -1,408 +1,409 @@@ + /* + * SAMSUNG EXYNOS Flattened Device Tree enabled machine + * + * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + #include + #include + #include ++#include + #include + #include + #include + #include + #include + #include + + #include + #include + #include + #include + #include + + #include -#include + + #include "common.h" + #include "mfc.h" + #include "regs-pmu.h" + + #define L2_AUX_VAL 0x7C470001 + #define L2_AUX_MASK 0xC200ffff + + static struct map_desc exynos4_iodesc[] __initdata = { + { + .virtual = (unsigned long)S3C_VA_SYS, + .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_TIMER, + .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_WATCHDOG, + .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SROMC, + .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SYSTIMER, + .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_PMU, + .pfn = __phys_to_pfn(EXYNOS4_PA_PMU), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_COMBINER_BASE, + .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_GIC_CPU, + .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_GIC_DIST, + .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_CMU, + .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), + .length = SZ_128K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_COREPERI_BASE, + .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI), + .length = SZ_8K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_L2CC, + .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_DMC0, + .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_DMC1, + .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_USB_HSPHY, + .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), + .length = SZ_4K, + .type = MT_DEVICE, + }, + }; + + static struct map_desc exynos4_iodesc0[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM, + .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0), + .length = SZ_4K, + .type = MT_DEVICE, + }, + }; + + static struct map_desc exynos4_iodesc1[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM, + .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1), + .length = SZ_4K, + .type = MT_DEVICE, + }, + }; + + static struct map_desc exynos4210_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM_NS, + .pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS), + .length = SZ_4K, + .type = MT_DEVICE, + }, + }; + + static struct map_desc exynos4x12_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM_NS, + .pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS), + .length = SZ_4K, + .type = MT_DEVICE, + }, + }; + + static struct map_desc exynos5250_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSRAM_NS, + .pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS), + .length = SZ_4K, + .type = MT_DEVICE, + }, + }; + + static struct map_desc exynos5_iodesc[] __initdata = { + { + .virtual = (unsigned long)S3C_VA_SYS, + .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_TIMER, + .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S3C_VA_WATCHDOG, + .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SROMC, + .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SYSRAM, + .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_CMU, + .pfn = __phys_to_pfn(EXYNOS5_PA_CMU), + .length = 144 * SZ_1K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_PMU, + .pfn = __phys_to_pfn(EXYNOS5_PA_PMU), + .length = SZ_64K, + .type = MT_DEVICE, + }, + }; + + void exynos_restart(enum reboot_mode mode, const char *cmd) + { + struct device_node *np; + u32 val = 0x1; + void __iomem *addr = EXYNOS_SWRESET; + + if (of_machine_is_compatible("samsung,exynos5440")) { + u32 status; + np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock"); + + addr = of_iomap(np, 0) + 0xbc; + status = __raw_readl(addr); + + addr = of_iomap(np, 0) + 0xcc; + val = __raw_readl(addr); + + val = (val & 0xffff0000) | (status & 0xffff); + } + + __raw_writel(val, addr); + } + + static struct platform_device exynos_cpuidle = { + .name = "exynos_cpuidle", + .id = -1, + }; + + void __init exynos_cpuidle_init(void) + { + platform_device_register(&exynos_cpuidle); + } + + void __init exynos_cpufreq_init(void) + { + platform_device_register_simple("exynos-cpufreq", -1, NULL, 0); + } + + void __init exynos_init_late(void) + { + if (of_machine_is_compatible("samsung,exynos5440")) + /* to be supported later */ + return; + + pm_genpd_poweroff_unused(); ++ exynos_pm_init(); + } + + static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, + int depth, void *data) + { + struct map_desc iodesc; + __be32 *reg; + unsigned long len; + + if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") && + !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock")) + return 0; + + reg = of_get_flat_dt_prop(node, "reg", &len); + if (reg == NULL || len != (sizeof(unsigned long) * 2)) + return 0; + + iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0])); + iodesc.length = be32_to_cpu(reg[1]) - 1; + iodesc.virtual = (unsigned long)S5P_VA_CHIPID; + iodesc.type = MT_DEVICE; + iotable_init(&iodesc, 1); + return 1; + } + + /* + * exynos_map_io + * + * register the standard cpu IO areas + */ + static void __init exynos_map_io(void) + { + if (soc_is_exynos4()) + iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); + + if (soc_is_exynos5()) + iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); + + if (soc_is_exynos4210()) { + if (samsung_rev() == EXYNOS4210_REV_0) + iotable_init(exynos4_iodesc0, + ARRAY_SIZE(exynos4_iodesc0)); + else + iotable_init(exynos4_iodesc1, + ARRAY_SIZE(exynos4_iodesc1)); + iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc)); + } + if (soc_is_exynos4212() || soc_is_exynos4412()) + iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc)); + if (soc_is_exynos5250()) + iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); + } + + void __init exynos_init_io(void) + { + debug_ll_io_init(); + + of_scan_flat_dt(exynos_fdt_map_chipid, NULL); + + /* detect cpu id and rev. */ + s5p_init_cpu(S5P_VA_CHIPID); + + exynos_map_io(); + } + + struct bus_type exynos_subsys = { + .name = "exynos-core", + .dev_name = "exynos-core", + }; + + static int __init exynos_core_init(void) + { + return subsys_system_register(&exynos_subsys, NULL); + } + core_initcall(exynos_core_init); + + static int __init exynos4_l2x0_cache_init(void) + { + int ret; + + ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); + if (ret) + return ret; + + l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); + clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); + return 0; + } + early_initcall(exynos4_l2x0_cache_init); + + static void __init exynos_dt_machine_init(void) + { + struct device_node *i2c_np; + const char *i2c_compat = "samsung,s3c2440-i2c"; + unsigned int tmp; + int id; + + /* + * Exynos5's legacy i2c controller and new high speed i2c + * controller have muxed interrupt sources. By default the + * interrupts for 4-channel HS-I2C controller are enabled. + * If node for first four channels of legacy i2c controller + * are available then re-configure the interrupts via the + * system register. + */ + if (soc_is_exynos5()) { + for_each_compatible_node(i2c_np, NULL, i2c_compat) { + if (of_device_is_available(i2c_np)) { + id = of_alias_get_id(i2c_np, "i2c"); + if (id < 4) { + tmp = readl(EXYNOS5_SYS_I2C_CFG); + writel(tmp & ~(0x1 << id), + EXYNOS5_SYS_I2C_CFG); + } + } + } + } + + exynos_cpuidle_init(); + exynos_cpufreq_init(); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + } + + static char const *exynos_dt_compat[] __initconst = { + "samsung,exynos4", + "samsung,exynos4210", + "samsung,exynos4212", + "samsung,exynos4412", + "samsung,exynos5", + "samsung,exynos5250", + "samsung,exynos5420", + "samsung,exynos5440", + NULL + }; + + static void __init exynos_reserve(void) + { + #ifdef CONFIG_S5P_DEV_MFC + int i; + char *mfc_mem[] = { + "samsung,mfc-v5", + "samsung,mfc-v6", + "samsung,mfc-v7", + }; + + for (i = 0; i < ARRAY_SIZE(mfc_mem); i++) + if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i])) + break; + #endif + } + + DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)") + /* Maintainer: Thomas Abraham */ + /* Maintainer: Kukjin Kim */ + .smp = smp_ops(exynos_smp_ops), + .map_io = exynos_init_io, + .init_early = exynos_firmware_init, + .init_machine = exynos_dt_machine_init, + .init_late = exynos_init_late, + .dt_compat = exynos_dt_compat, + .restart = exynos_restart, + .reserve = exynos_reserve, + MACHINE_END