From: Bharat Kumar Gogada Date: Tue, 9 Aug 2016 14:00:09 +0000 (+0530) Subject: PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory... X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=9cbbae2a62bce72c17aeb204efeec240f45c4f4f;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space Updating device tree documentation with prefetchable memory sapce. Configuration space shifted to 64-bit address space. Signed-off-by: Bharat Kumar Gogada Acked-by: Rob Herring Signed-off-by: Rob Herring --- diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt index 337fc97d18c9..3259798a1192 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt +++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt @@ -55,9 +55,10 @@ nwl_pcie: pcie@fd0e0000 { msi-parent = <&nwl_pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x0 0xe0000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; - ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>; + ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ + 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ pcie_intc: legacy-interrupt-controller { interrupt-controller;