From: Linus Torvalds Date: Fri, 6 Nov 2015 20:17:09 +0000 (-0800) Subject: Merge tag 'devicetree-for-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh... X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=9bbd4b9f38f56b4ee2c8ff268a1104ff38333e90;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git Merge tag 'devicetree-for-4.4' of git://git./linux/kernel/git/robh/linux Pull DeviceTree updates from Rob Herring: "A fairly large (by DT standards) pull request this time with the majority being some overdue moving DT binding docs around to consolidate similar bindings. - DT binding doc consolidation moving similar bindings to common locations. The majority of these are display related which were scattered in video/, fb/, drm/, gpu/, and panel/ directories. - Add new config option, CONFIG_OF_ALL_DTBS, to enable building all dtbs in the tree for most arches with dts files (except powerpc for now). - OF_IRQ=n fixes for user enabled CONFIG_OF. - of_node_put ref counting fixes from Julia Lawall. - Common DT binding for wakeup-source and deprecation of all similar bindings. - DT binding for PXA LCD controller. - Allow ignoring failed PCI resource translations in order to ignore 64-bit addresses on non-LPAE 32-bit kernels. - Support setting the NUMA node from DT instead of only from parent device. - Couple of earlycon DT parsing fixes for address and options" * tag 'devicetree-for-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (45 commits) MAINTAINERS: update DT binding doc locations devicetree: add Sigma Designs vendor prefix of: simplify arch_find_n_match_cpu_physical_id() function Documentation: arm: Fixed typo in socfpga fpga mgr example Documentation: devicetree: fix reference to legacy wakeup properties Documentation: devicetree: standardize/consolidate on "wakeup-source" property drivers: of: removing assignment of 0 to static variable xtensa: enable building of all dtbs mips: enable building of all dtbs metag: enable building of all dtbs metag: use common make variables for dtb builds h8300: enable building of all dtbs arm64: enable building of all dtbs arm: enable building of all dtbs arc: enable building of all dtbs arc: use common make variables for dtb builds of: add config option to enable building of all dtbs of/fdt: fix error checking for earlycon address of/overlay: add missing of_node_put of/platform: add missing of_node_put ... --- 9bbd4b9f38f56b4ee2c8ff268a1104ff38333e90 diff --cc Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt index 000000000000,2da059a4790c..cc56021eb60b mode 000000,100644..100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt @@@ -1,0 -1,152 +1,168 @@@ + * ARM Generic Interrupt Controller + + ARM SMP cores are often associated with a GIC, providing per processor + interrupts (PPI), shared processor interrupts (SPI) and software + generated interrupts (SGI). + + Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. + Secondary GICs are cascaded into the upward interrupt controller and do not + have PPIs or SGIs. + + Main node required properties: + + - compatible : should be one of: - "arm,gic-400" ++ "arm,arm1176jzf-devchip-gic" ++ "arm,arm11mp-gic" + "arm,cortex-a15-gic" - "arm,cortex-a9-gic" + "arm,cortex-a7-gic" - "arm,arm11mp-gic" ++ "arm,cortex-a9-gic" ++ "arm,gic-400" ++ "arm,pl390" + "brcm,brahma-b15-gic" - "arm,arm1176jzf-devchip-gic" + "qcom,msm-8660-qgic" + "qcom,msm-qgic2" + - interrupt-controller : Identifies the node as an interrupt controller + - #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The type shall be a and the value shall be 3. + + The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI + interrupts. + + The 2nd cell contains the interrupt number for the interrupt type. + SPI interrupts are in the range [0-987]. PPI interrupts are in the + range [0-15]. + + The 3rd cell is the flags, encoded as follows: + bits[3:0] trigger type and level flags. + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered (invalid for SPIs) + 4 = active high level-sensitive + 8 = active low level-sensitive (invalid for SPIs). + bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of + the 8 possible cpus attached to the GIC. A bit set to '1' indicated + the interrupt is wired to that CPU. Only valid for PPI interrupts. + Also note that the configurability of PPI interrupts is IMPLEMENTATION + DEFINED and as such not guaranteed to be present (most SoC available + in 2014 seem to ignore the setting of this flag and use the hardware + default value). + + - reg : Specifies base physical address(s) and size of the GIC registers. The + first region is the GIC distributor register base and size. The 2nd region is + the GIC cpu interface register base and size. + + Optional + - interrupts : Interrupt source of the parent interrupt controller on + secondary GICs, or VGIC maintenance interrupt on primary GIC (see + below). + + - cpu-offset : per-cpu offset within the distributor and cpu interface + regions, used when the GIC doesn't have banked registers. The offset is + cpu-offset * cpu-nr. + ++- clocks : List of phandle and clock-specific pairs, one for each entry ++ in clock-names. ++- clock-names : List of names for the GIC clock input(s). Valid clock names ++ depend on the GIC variant: ++ "ic_clk" (for "arm,arm11mp-gic") ++ "PERIPHCLKEN" (for "arm,cortex-a15-gic") ++ "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic") ++ "clk" (for "arm,gic-400") ++ "gclk" (for "arm,pl390") ++ ++- power-domains : A phandle and PM domain specifier as defined by bindings of ++ the power controller specified by phandle, used when the GIC ++ is part of a Power or Clock Domain. ++ ++ + Example: + + intc: interrupt-controller@fff11000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xfff11000 0x1000>, + <0xfff10100 0x100>; + }; + + + * GIC virtualization extensions (VGIC) + + For ARM cores that support the virtualization extensions, additional + properties must be described (they only exist if the GIC is the + primary interrupt controller). + + Required properties: + + - reg : Additional regions specifying the base physical address and + size of the VGIC registers. The first additional region is the GIC + virtual interface control register base and size. The 2nd additional + region is the GIC virtual cpu interface register base and size. + + - interrupts : VGIC maintenance interrupt. + + Example: + + interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x2c001000 0x1000>, + <0x2c002000 0x1000>, + <0x2c004000 0x2000>, + <0x2c006000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + + * GICv2m extension for MSI/MSI-x support (Optional) + + Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). + This is enabled by specifying v2m sub-node(s). + + Required properties: + + - compatible : The value here should contain "arm,gic-v2m-frame". + + - msi-controller : Identifies the node as an MSI controller. + + - reg : GICv2m MSI interface register base and size + + Optional properties: + + - arm,msi-base-spi : When the MSI_TYPER register contains an incorrect + value, this property should contain the SPI base of + the MSI frame, overriding the HW value. + + - arm,msi-num-spis : When the MSI_TYPER register contains an incorrect + value, this property should contain the number of + SPIs assigned to the frame, overriding the HW value. + + Example: + + interrupt-controller@e1101000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + interrupts = <1 8 0xf04>; + ranges = <0 0 0 0xe1100000 0 0x100000>; + reg = <0x0 0xe1110000 0 0x01000>, + <0x0 0xe112f000 0 0x02000>, + <0x0 0xe1140000 0 0x10000>, + <0x0 0xe1160000 0 0x10000>; + v2m0: v2m@0x8000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x80000 0 0x1000>; + }; + + .... + + v2mN: v2m@0x9000 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x90000 0 0x1000>; + }; + }; diff --cc Documentation/devicetree/bindings/leds/backlight/pm8941-wled.txt index 000000000000,424f8444a6cd..e5b294dafc58 mode 000000,100644..100644 --- a/Documentation/devicetree/bindings/leds/backlight/pm8941-wled.txt +++ b/Documentation/devicetree/bindings/leds/backlight/pm8941-wled.txt @@@ -1,0 -1,40 +1,42 @@@ + Binding for Qualcomm PM8941 WLED driver + + Required properties: + - compatible: should be "qcom,pm8941-wled" + - reg: slave address + + Optional properties: ++- default-brightness: brightness value on boot, value from: 0-4095 ++ default: 2048 + - label: The name of the backlight device + - qcom,cs-out: bool; enable current sink output + - qcom,cabc: bool; enable content adaptive backlight control + - qcom,ext-gen: bool; use externally generated modulator signal to dim + - qcom,current-limit: mA; per-string current limit; value from 0 to 25 + default: 20mA + - qcom,current-boost-limit: mA; boost current limit; one of: + 105, 385, 525, 805, 980, 1260, 1400, 1680 + default: 805mA + - qcom,switching-freq: kHz; switching frequency; one of: + 600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371, + 1600, 1920, 2400, 3200, 4800, 9600, + default: 1600kHz + - qcom,ovp: V; Over-voltage protection limit; one of: + 27, 29, 32, 35 + default: 29V + - qcom,num-strings: #; number of led strings attached; value from 1 to 3 + default: 2 + + Example: + + pm8941-wled@d800 { + compatible = "qcom,pm8941-wled"; + reg = <0xd800>; + label = "backlight"; + + qcom,cs-out; + qcom,current-limit = <20>; + qcom,current-boost-limit = <805>; + qcom,switching-freq = <1600>; + qcom,ovp = <29>; + qcom,num-strings = <2>; + }; diff --cc Documentation/devicetree/bindings/vendor-prefixes.txt index a79185f78ccd,5a47e8895084..8c6cef73e0d7 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@@ -194,8 -192,8 +195,9 @@@ sbs Smart Battery Syste schindler Schindler seagate Seagate Technology PLC semtech Semtech Corporation +sgx SGX Sensortech sharp Sharp Corporation + sigma Sigma Designs, Inc. sil Silicon Image silabs Silicon Laboratories siliconmitus Silicon Mitus, Inc. diff --cc MAINTAINERS index e2b8cbbfcd8d,e2aa9736fd0f..f56a10a3eabc --- a/MAINTAINERS +++ b/MAINTAINERS @@@ -3663,16 -3617,8 +3663,16 @@@ M: Philipp Zabel +L: dri-devel@lists.freedesktop.org +T: git git://github.com/patjak/drm-gma500 +S: Maintained +F: drivers/gpu/drm/gma500 +F: include/drm/gma500* + DRM DRIVERS FOR NVIDIA TEGRA M: Thierry Reding M: Terje Bergström diff --cc include/linux/of_irq.h index 65d969246a4d,580818d90475..039f2eec49ce --- a/include/linux/of_irq.h +++ b/include/linux/of_irq.h @@@ -46,11 -46,7 +46,12 @@@ extern int of_irq_get(struct device_nod extern int of_irq_get_byname(struct device_node *dev, const char *name); extern int of_irq_to_resource_table(struct device_node *dev, struct resource *res, int nr_irqs); +extern struct irq_domain *of_msi_get_domain(struct device *dev, + struct device_node *np, + enum irq_domain_bus_token token); +extern struct irq_domain *of_msi_map_get_device_domain(struct device *dev, + u32 rid); + extern void of_msi_configure(struct device *dev, struct device_node *np); #else static inline int of_irq_count(struct device_node *dev) { @@@ -69,47 -65,25 +70,43 @@@ static inline int of_irq_to_resource_ta { return 0; } +static inline struct irq_domain *of_msi_get_domain(struct device *dev, + struct device_node *np, + enum irq_domain_bus_token token) +{ + return NULL; +} +static inline struct irq_domain *of_msi_map_get_device_domain(struct device *dev, + u32 rid) +{ + return NULL; +} + static inline void of_msi_configure(struct device *dev, struct device_node *np) + { + } #endif - #if defined(CONFIG_OF) + #if defined(CONFIG_OF_IRQ) || defined(CONFIG_SPARC) /* * irq_of_parse_and_map() is used by all OF enabled platforms; but SPARC * implements it differently. However, the prototype is the same for all, * so declare it here regardless of the CONFIG_OF_IRQ setting. */ extern unsigned int irq_of_parse_and_map(struct device_node *node, int index); - extern struct device_node *of_irq_find_parent(struct device_node *child); - extern void of_msi_configure(struct device *dev, struct device_node *np); +u32 of_msi_map_rid(struct device *dev, struct device_node *msi_np, u32 rid_in); - #else /* !CONFIG_OF */ + #else /* !CONFIG_OF && !CONFIG_SPARC */ static inline unsigned int irq_of_parse_and_map(struct device_node *dev, int index) { return 0; } + - static inline void *of_irq_find_parent(struct device_node *child) - { - return NULL; - } - +static inline u32 of_msi_map_rid(struct device *dev, + struct device_node *msi_np, u32 rid_in) +{ + return rid_in; +} #endif /* !CONFIG_OF */ #endif /* __OF_IRQ_H */