From: Arnd Bergmann <arnd@arndb.de>
Date: Fri, 23 Jun 2017 12:29:17 +0000 (+0200)
Subject: Merge tag 'mvebu-fixes-4.12-1' of git://git.infradead.org/linux-mvebu into next/dt64
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=9b3088135aba74c177529096a6925f3c0af077c2;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

Merge tag 'mvebu-fixes-4.12-1' of git://git.infradead.org/linux-mvebu into next/dt64

mvebu fixes for 4.12

Fix the interrupt description of the crypto node for device tree of
the Armada 7K/8K SoCs

* tag 'mvebu-fixes-4.12-1' of git://git.infradead.org/linux-mvebu:
  arm64: marvell: dts: fix interrupts in 7k/8k crypto nodes
---

9b3088135aba74c177529096a6925f3c0af077c2
diff --cc arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index aec5f94423dd,b4bc42ece754..f611e843094c
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@@ -261,17 -231,16 +261,16 @@@
  			cpm_crypto: crypto@800000 {
  				compatible = "inside-secure,safexcel-eip197";
  				reg = <0x800000 0x200000>;
- 				interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
- 				| IRQ_TYPE_LEVEL_HIGH)>,
 -				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 -					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 -					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 -					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 -					     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 -					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
++				interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
 +					     <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
 +					     <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
 +					     <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
 +					     <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
 +					     <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
  				interrupt-names = "mem", "ring0", "ring1",
  				"ring2", "ring3", "eip";
 -				clocks = <&cpm_syscon0 1 26>;
 -				status = "disabled";
 +				clocks = <&cpm_clk 1 26>;
 +				dma-mask = <0xff 0xffffffff>;
  			};
  		};
  
diff --cc arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 9daf1e17bdfe,6e2058847ddc..84d3bd80eb51
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@@ -252,24 -221,15 +252,23 @@@
  			cps_crypto: crypto@800000 {
  				compatible = "inside-secure,safexcel-eip197";
  				reg = <0x800000 0x200000>;
- 				interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
- 				| IRQ_TYPE_LEVEL_HIGH)>,
 -				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 -					     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 -					     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 -					     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
 -					     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
 -					     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
++				interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
 +					     <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
 +					     <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
 +					     <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
 +					     <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
 +					     <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
  				interrupt-names = "mem", "ring0", "ring1",
  						  "ring2", "ring3", "eip";
 -				clocks = <&cps_syscon0 1 26>;
 +				clocks = <&cps_clk 1 26>;
 +				dma-mask = <0xff 0xffffffff>;
 +				/*
 +				 * The cryptographic engine found on the cp110
 +				 * master is enabled by default at the SoC
 +				 * level. Because it is not possible as of now
 +				 * to enable two cryptographic engines in
 +				 * parallel, disable this one by default.
 +				 */
  				status = "disabled";
  			};
  		};