From: Liu Shuo Date: Fri, 9 Dec 2011 09:42:54 +0000 (+0800) Subject: mtd: fsl_elbc_nand: set Nand flash page address to FBAR and FPAR correctly X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=9ae84fe8c18cabc348b9c7cd1e98419cd0cbf481;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git mtd: fsl_elbc_nand: set Nand flash page address to FBAR and FPAR correctly If we use the Nand flash chip whose number of pages in a block is greater than 64(for large page), we must treat the low bit of FBAR as being the high bit of the page address due to the limitation of FCM, it simply uses the low 6-bits (for large page) of the combined block/page address as the FPAR component, rather than considering the actual block size. Signed-off-by: Liu Shuo Signed-off-by: Jerry Huang Signed-off-by: Tang Yuantian Signed-off-by: Li Yang Acked-by: Scott Wood Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 7db573e9bf78..d29479abe504 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -166,15 +166,22 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) elbc_fcm_ctrl->page = page_addr; - out_be32(&lbc->fbar, - page_addr >> (chip->phys_erase_shift - chip->page_shift)); - if (priv->page_size) { + /* + * large page size chip : FPAR[PI] save the lowest 6 bits, + * FBAR[BLK] save the other bits. + */ + out_be32(&lbc->fbar, page_addr >> 6); out_be32(&lbc->fpar, ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | (oob ? FPAR_LP_MS : 0) | column); buf_num = (page_addr & 1) << 2; } else { + /* + * small page size chip : FPAR[PI] save the lowest 5 bits, + * FBAR[BLK] save the other bits. + */ + out_be32(&lbc->fbar, page_addr >> 5); out_be32(&lbc->fpar, ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | (oob ? FPAR_SP_MS : 0) | column);