From: Maciej W. Rozycki <macro@linux-mips.org>
Date: Wed, 27 May 2015 13:15:20 +0000 (+0100)
Subject: MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=9a20b09285bbd75ccc2ca78233241f8e31d54a28;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation

Replace an explicit barrier with a useful processor instruction in TLB
invalidation, following several other such cases elsewhere in
`tlb-r3k.c'.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10196/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index 49b7132069d0..2b75b8f880ed 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -45,10 +45,10 @@ static void local_flush_tlb_from(int entry)
 
 	old_ctx = read_c0_entryhi() & ASID_MASK;
 	write_c0_entrylo0(0);
-	for (; entry < current_cpu_data.tlbsize; entry++) {
+	while (entry < current_cpu_data.tlbsize) {
 		write_c0_index(entry << 8);
 		write_c0_entryhi((entry | 0x80000) << 12);
-		BARRIER;
+		entry++;				/* BARRIER */
 		tlb_write_indexed();
 	}
 	write_c0_entryhi(old_ctx);