From: Jordan Justen Date: Mon, 7 Mar 2016 07:30:28 +0000 (-0800) Subject: drm/i915: Move Haswell registers to separate whitelist table X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=99c5aeca94a506a2b279022fae5de3f8606730bd;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/i915: Move Haswell registers to separate whitelist table Now that we can whitelist registers only on Haswell, move HSW_SCRATCH1 and HSW_ROW_CHICKEN3 into a separate Haswell only table. Signed-off-by: Jordan Justen Cc: Francisco Jerez Reviewed-by: Francisco Jerez Signed-off-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/1457335830-30923-4-git-send-email-jordan.l.justen@intel.com --- diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index ce753d3a817f..6c81c700d746 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -472,6 +472,9 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = { REG32(GEN7_L3SQCREG1), REG32(GEN7_L3CNTLREG2), REG32(GEN7_L3CNTLREG3), +}; + +static const struct drm_i915_reg_descriptor hsw_render_regs[] = { REG32(HSW_SCRATCH1, .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, .value = 0), @@ -519,6 +522,7 @@ static const struct drm_i915_reg_table ivb_blt_reg_tables[] = { static const struct drm_i915_reg_table hsw_render_reg_tables[] = { { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false }, + { hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false }, { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true }, };