From: David S. Miller <davem@davemloft.net>
Date: Mon, 27 Feb 2006 04:37:41 +0000 (-0800)
Subject: [SPARC64]: Use 13-bit context size always.
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=97c4b6f95afadea5846b78ce589d25de2a245c56;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

[SPARC64]: Use 13-bit context size always.

We no longer have the problems that require using the smaller
sizes.

Signed-off-by: David S. Miller <davem@davemloft.net>
---

diff --git a/include/asm-sparc64/mmu.h b/include/asm-sparc64/mmu.h
index 1504d303a1d5..da14a9bf0ed6 100644
--- a/include/asm-sparc64/mmu.h
+++ b/include/asm-sparc64/mmu.h
@@ -6,19 +6,7 @@
 #include <asm/const.h>
 #include <asm/hypervisor.h>
 
-/*
- * For the 8k pagesize kernel, use only 10 hw context bits to optimize some
- * shifts in the fast tlbmiss handlers, instead of all 13 bits (specifically
- * for vpte offset calculation). For other pagesizes, this optimization in
- * the tlbhandlers can not be done; but still, all 13 bits can not be used
- * because the tlb handlers use "andcc" instruction which sign extends 13
- * bit arguments.
- */
-#if PAGE_SHIFT == 13
-#define CTX_NR_BITS		10
-#else
-#define CTX_NR_BITS		12
-#endif
+#define CTX_NR_BITS		13
 
 #define TAG_CONTEXT_BITS	((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))