From: Masahiro Yamada Date: Sat, 23 Jan 2016 08:55:30 +0000 (+0900) Subject: ARM: tegra: Remove redundant ARM_L1_CACHE_SHIFT_6 select X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=955d809bdeaea3663cf6ac1ee72cd50775bbab9d;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git ARM: tegra: Remove redundant ARM_L1_CACHE_SHIFT_6 select These two are both ARMv7 SoCs. They need not explicitly select ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7. Refer to commit a092f2b15399 ("ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs"). Signed-off-by: Masahiro Yamada Signed-off-by: Thierry Reding --- diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index d0c3c3e085e3..03089ad2fc65 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -31,7 +31,6 @@ config ARCH_TEGRA_3x_SOC config ARCH_TEGRA_114_SOC bool "Enable support for Tegra114 family" select ARM_ERRATA_798181 if SMP - select ARM_L1_CACHE_SHIFT_6 select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA114 select TEGRA_TIMER @@ -41,7 +40,6 @@ config ARCH_TEGRA_114_SOC config ARCH_TEGRA_124_SOC bool "Enable support for Tegra124 family" - select ARM_L1_CACHE_SHIFT_6 select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA124 select TEGRA_TIMER