From: James Hogan Date: Fri, 15 Apr 2016 09:07:26 +0000 (+0100) Subject: MIPS: Fix MSA assembly warnings X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=92e9953c5865b47281d74d43f08d7cecde11e58a;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git MIPS: Fix MSA assembly warnings Building an MSA capable kernel with a toolchain that supports MSA produces warnings such as this: arch/mips/kernel/r4k_fpu.S:229: Warning: the `msa' extension requires 64-bit FPRs This is due to ".set msa" without ".set fp=64" in the non doubleword MSA load/store macros, since MSA requires the 64-bit FPU registers (FR=1). Add the missing fp=64 in these macros to silence the warnings. Signed-off-by: James Hogan Cc: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13063/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h index 637fccab5604..6741673c92ca 100644 --- a/arch/mips/include/asm/asmmacro.h +++ b/arch/mips/include/asm/asmmacro.h @@ -235,6 +235,7 @@ .macro ld_b wd, off, base .set push .set mips32r2 + .set fp=64 .set msa ld.b $w\wd, \off(\base) .set pop @@ -243,6 +244,7 @@ .macro ld_h wd, off, base .set push .set mips32r2 + .set fp=64 .set msa ld.h $w\wd, \off(\base) .set pop @@ -251,6 +253,7 @@ .macro ld_w wd, off, base .set push .set mips32r2 + .set fp=64 .set msa ld.w $w\wd, \off(\base) .set pop @@ -268,6 +271,7 @@ .macro st_b wd, off, base .set push .set mips32r2 + .set fp=64 .set msa st.b $w\wd, \off(\base) .set pop @@ -276,6 +280,7 @@ .macro st_h wd, off, base .set push .set mips32r2 + .set fp=64 .set msa st.h $w\wd, \off(\base) .set pop @@ -284,6 +289,7 @@ .macro st_w wd, off, base .set push .set mips32r2 + .set fp=64 .set msa st.w $w\wd, \off(\base) .set pop