From: Choonghoon Park Date: Fri, 15 Jun 2018 08:39:57 +0000 (+0900) Subject: arm64: dts: modify fields for setting hafm boost frequency X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=92775a26f09289adafd3631d902b8d9f5f406db1;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git arm64: dts: modify fields for setting hafm boost frequency Change-Id: I77de428cc7ef3276bc100ddf3f2ee2bc22f89d35 --- diff --git a/arch/arm64/boot/dts/exynos/exynos9820.dts b/arch/arm64/boot/dts/exynos/exynos9820.dts new file mode 100644 index 000000000000..47472670daf5 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos9820.dts @@ -0,0 +1,5866 @@ +/* + * SAMSUNG EXYNOS9820 SoC device tree source + * + * Copyright (c) 2018 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SAMSUNG EXYNOS9820 SoC device nodes are listed in this file. + * EXYNOS based board files can include this file and provide + * values for board specfic bindings. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include +#include +#include +#include +#include "exynos9820-pinctrl.dtsi" +#include "exynos9820-rmem.dtsi" +#include "exynos9820-sysmmu.dtsi" +#include "exynos9820-debug.dtsi" +#include +#include +#include "exynos9820-pm-domains.dtsi" +#include +#include +#include +#include "exynos9820-camera.dtsi" +#include +#include "exynos9820-pmucal-dbg.dtsi" +#include "exynos9820-mfc.dtsi" + +/ { + compatible = "samsung,armv8", "samsung,exynos9820"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + pinctrl4 = &pinctrl_4; + pinctrl5 = &pinctrl_5; + pinctrl6 = &pinctrl_6; + pinctrl7 = &pinctrl_7; + uart0 = &serial_0; + mshc2 = &dwmmc_2; + usi0 = &usi_0; + usi1 = &usi_0_i2c; + usi2 = &usi_1; + usi3 = &usi_1_i2c; + usi4 = &usi_2; + usi5 = &usi_2_i2c; + usi6 = &usi_3; + usi7 = &usi_3_i2c; + usi8 = &usi_4; + usi9 = &usi_4_i2c; + usi10 = &usi_5; + usi11 = &usi_5_i2c; + usi12 = &usi_6; + usi13 = &usi_6_i2c; + usi14 = &usi_7; + usi15 = &usi_7_i2c; + usi16 = &usi_8; + usi17 = &usi_8_i2c; + usi18 = &usi_9; + usi19 = &usi_9_i2c; + usi20 = &usi_10; + usi21 = &usi_10_i2c; + usi22 = &usi_11; + usi23 = &usi_11_i2c; + usi24 = &usi_12; + usi25 = &usi_12_i2c; + usi26 = &usi_13; + usi27 = &usi_13_i2c; + usi28 = &usi_14; + usi29 = &usi_14_i2c; + usi30 = &usi_15; + usi31 = &usi_15_i2c; + usi32 = &usi_16; + usi33 = &usi_17; + usi34 = &usi_17_i2c; + usi35 = &usi_00_cmgp; + usi36 = &usi_00_cmgp_i2c; + usi37 = &usi_01_cmgp; + usi38 = &usi_01_cmgp_i2c; + usi39 = &usi_02_cmgp; + usi40 = &usi_02_cmgp_i2c; + usi41 = &usi_03_cmgp; + usi42 = &usi_03_cmgp_i2c; + usi43 = &usi_i2c_cam_0; + usi44 = &usi_i2c_cam_1; + usi45 = &usi_i2c_cam_2; + usi46 = &usi_i2c_cam_3; + usi47 = &usi_spi_cam_0; + usi48 = &usi_uart_dbg; + usi49 = &usi_uart_bt; + hsi2c0 = &hsi2c_0; + hsi2c1 = &hsi2c_1; + hsi2c2 = &hsi2c_2; + hsi2c3 = &hsi2c_3; + hsi2c4 = &hsi2c_4; + hsi2c5 = &hsi2c_5; + hsi2c6 = &hsi2c_6; + hsi2c7 = &hsi2c_7; + hsi2c8 = &hsi2c_8; + hsi2c9 = &hsi2c_9; + hsi2c10 = &hsi2c_10; + hsi2c11 = &hsi2c_11; + hsi2c12 = &hsi2c_12; + hsi2c13 = &hsi2c_13; + hsi2c14 = &hsi2c_14; + hsi2c15 = &hsi2c_15; + hsi2c16 = &hsi2c_16; + hsi2c17 = &hsi2c_17; + hsi2c18 = &hsi2c_18; + hsi2c19 = &hsi2c_19; + hsi2c20 = &hsi2c_20; + hsi2c21 = &hsi2c_21; + hsi2c22 = &hsi2c_22; + hsi2c23 = &hsi2c_23; + hsi2c24 = &hsi2c_24; + hsi2c25 = &hsi2c_25; + hsi2c26 = &hsi2c_26; + hsi2c27 = &hsi2c_27; + hsi2c28 = &hsi2c_28; + hsi2c29 = &hsi2c_29; + hsi2c30 = &hsi2c_30; + hsi2c31 = &hsi2c_31; + hsi2c32 = &hsi2c_32; + hsi2c33 = &hsi2c_33; + hsi2c34 = &hsi2c_34; + hsi2c35 = &hsi2c_35; + hsi2c36 = &hsi2c_36; + hsi2c37 = &hsi2c_37; + hsi2c38 = &hsi2c_38; + hsi2c39 = &hsi2c_39; + hsi2c40 = &hsi2c_40; + hsi2c41 = &hsi2c_41; + hsi2c42 = &hsi2c_42; + hsi2c43 = &hsi2c_43; + hsi2c44 = &hsi2c_44; + hsi2c45 = &hsi2c_45; + hsi2c46 = &hsi2c_46; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + spi5 = &spi_5; + spi6 = &spi_6; + spi7 = &spi_7; + spi8 = &spi_8; + spi9 = &spi_9; + spi10 = &spi_10; + spi11 = &spi_11; + spi12 = &spi_12; + spi13 = &spi_13; + spi14 = &spi_14; + spi15 = &spi_15; + spi16 = &spi_16; + spi17 = &spi_17; + spi18 = &spi_18; + spi19 = &spi_19; + spi20 = &spi_20; + spi21 = &spi_21; + spi22 = &spi_22; + uart1 = &serial_1; + uart2 = &serial_2; + uart3 = &serial_3; + uart4 = &serial_4; + uart5 = &serial_5; + uart6 = &serial_6; + uart7 = &serial_7; + uart8 = &serial_8; + uart9 = &serial_9; + uart10 = &serial_10; + uart11 = &serial_11; + uart12 = &serial_12; + uart13 = &serial_13; + uart14 = &serial_14; + uart15 = &serial_15; + uart16 = &serial_16; + uart17 = &serial_17; + uart18 = &serial_18; + uart19 = &serial_19; + uart20 = &serial_20; + uart21 = &serial_21; + uart22 = &serial_22; + uart23 = &serial_23; + + dpp0 = &dpp_0; + dpp1 = &dpp_1; + dpp2 = &dpp_2; + dpp3 = &dpp_3; + dpp4 = &dpp_4; + dpp5 = &dpp_5; + dsim0 = &dsim_0; + displayport = &displayport; + decon0 = &decon_f; + decon2 = &decon_t; + fmp0 = &fmp_0; + mfc0 = &mfc_0; + scaler0 = &scaler_0; + }; + + firmware { + android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/platform/13d60000.ufs/by-name/system"; + type = "ext4"; + mnt_flags = "ro"; + fsmgr_flags = "wait"; + status = "disabled"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/13d60000.ufs/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro"; + fsmgr_flags = "wait"; + status = "okay"; + }; + }; + }; + }; + + chipid@10000000 { + compatible = "samsung,exynos9810-chipid"; + reg = <0x0 0x10000000 0x100>; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 INTREQ__CPUCL2_PMUIRQ_0 4>, + <0 INTREQ__CPUCL2_PMUIRQ_1 4>, + <0 INTREQ__CPUCL0_PMUIRQ_0 4>, + <0 INTREQ__CPUCL0_PMUIRQ_1 4>, + <0 INTREQ__CPUCL0_PMUIRQ_2 4>, + <0 INTREQ__CPUCL0_PMUIRQ_3 4>, + <0 INTREQ__CPUCL0_PMUIRQ_4 4>, + <0 INTREQ__CPUCL0_PMUIRQ_5 4>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + coregroup0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + coregroup1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + }; + }; + + cluster1 { + coregroup0 { + core0 { + cpu = <&cpu6>; + }; + core1 { + cpu = <&cpu7>; + }; + }; + }; + + }; + + cpu0: cpu@0000 { + device_type = "cpu"; + compatible = "arm,ananke", "arm,armv8"; + reg = <0x0 0x0000>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + sched-energy-costs = <&A55_CPU_COST &A55_COREGROUP_COST + &DSU_CLUSTER_COST>; + sched-energy-data = <&ANANKE_ENERGY>; + }; + cpu1: cpu@0001 { + device_type = "cpu"; + compatible = "arm,ananke", "arm,armv8"; + reg = <0x0 0x0001>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + sched-energy-costs = <&A55_CPU_COST &A55_COREGROUP_COST + &DSU_CLUSTER_COST>; + sched-energy-data = <&ANANKE_ENERGY>; + }; + cpu2: cpu@0002 { + device_type = "cpu"; + compatible = "arm,ananke", "arm,armv8"; + reg = <0x0 0x0002>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + sched-energy-costs = <&A55_CPU_COST &A55_COREGROUP_COST + &DSU_CLUSTER_COST>; + sched-energy-data = <&ANANKE_ENERGY>; + }; + cpu3: cpu@0003 { + device_type = "cpu"; + compatible = "arm,ananke", "arm,armv8"; + reg = <0x0 0x0003>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + sched-energy-costs = <&A55_CPU_COST &A55_COREGROUP_COST + &DSU_CLUSTER_COST>; + sched-energy-data = <&ANANKE_ENERGY>; + }; + cpu4: cpu@0004 { + device_type = "cpu"; + compatible = "arm,prometheus", "arm,armv8"; + reg = <0x0 0x0004>; + enable-method = "psci"; + cpu-idle-states = <&PROMETHEUS_CPU_SLEEP>; + sched-energy-costs = <&A75_CPU_COST &A75_COREGROUP_COST + &DSU_CLUSTER_COST>; + sched-energy-data = <&PROMETHEUS_ENERGY>; + }; + cpu5: cpu@0005 { + device_type = "cpu"; + compatible = "arm,prometheus", "arm,armv8"; + reg = <0x0 0x0005>; + enable-method = "psci"; + cpu-idle-states = <&PROMETHEUS_CPU_SLEEP>; + sched-energy-costs = <&A75_CPU_COST &A75_COREGROUP_COST + &DSU_CLUSTER_COST>; + sched-energy-data = <&PROMETHEUS_ENERGY>; + }; + + cpu6: cpu@0100 { + device_type = "cpu"; + compatible = "arm,cheetah", "arm,armv8"; + reg = <0x0 0x0100>; + enable-method = "psci"; + cpu-idle-states = <&CHEETAH_CPU_SLEEP>; + sched-energy-costs = <&CH_CPU_COST &CH_COREGROUP_COST + &CH_CLUSTER_COST>; + sched-energy-data = <&CHEETAH_ENERGY>; + }; + cpu7: cpu@0101 { + device_type = "cpu"; + compatible = "arm,cheetah", "arm,armv8"; + reg = <0x0 0x0101>; + enable-method = "psci"; + cpu-idle-states = <&CHEETAH_CPU_SLEEP>; + sched-energy-costs = <&CH_CPU_COST &CH_COREGROUP_COST + &CH_CLUSTER_COST>; + sched-energy-data = <&CHEETAH_ENERGY>; + }; + + idle-states { + entry-method = "arm,psci"; + + ANANKE_CPU_SLEEP: ananke-cpu-sleep { + idle-state-name = "c2"; + compatible = "exynos,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <70>; + exit-latency-us = <160>; + min-residency-us = <2000>; + status = "okay"; + }; + + PROMETHEUS_CPU_SLEEP: prometheus-cpu-sleep { + idle-state-name = "c2"; + compatible = "exynos,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <150>; + exit-latency-us = <190>; + min-residency-us = <2500>; + status = "okay"; + }; + + CHEETAH_CPU_SLEEP: cheetah-cpu-sleep { + idle-state-name = "c2"; + compatible = "exynos,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <235>; + exit-latency-us = <220>; + min-residency-us = <3500>; + status = "okay"; + }; + }; + + energy-data { + ANANKE_ENERGY: ananke-energy { + capacity-mips = <271>; + power-coefficient = <91>; + }; + PROMETHEUS_ENERGY: prometheus-energy { + capacity-mips = <530>; + power-coefficient = <261>; + }; + CHEETAH_ENERGY: cheetah-energy { + capacity-mips = <889>; + power-coefficient = <870>; + }; + }; + + energy-costs { + A55_CPU_COST: core-core0 { + busy-cost-data = < + 44 24 + 55 32 + 65 42 + 81 59 + 95 76 + 105 94 + 116 115 + 130 153 + 146 200 + 159 238 + 174 306 + 185 393 + 195 496 + >; + idle-cost-data = < + 1 + 1 + 0 + >; + }; + A75_CPU_COST: core-core1 { + busy-cost-data = < + 153 113 + 177 131 + 198 152 + 226 186 + 250 221 + 287 274 + 330 360 + 354 420 + 372 466 + 397 541 + 421 640 + 446 804 + 470 1005 + >; + idle-cost-data = < + 4 + 4 + 0 + >; + }; + CH_CPU_COST: core-core2 { + busy-cost-data = < + 246 431 + 287 483 + 323 523 + 369 619 + 410 647 + 451 748 + 492 840 + 543 994 + 573 1150 + 614 1323 + 655 1530 + 717 1850 + 778 2205 + 819 2525 + 881 3325 + 922 4133 + 973 5150 + 1024 6335 + >; + idle-cost-data = < + 10 + 10 + 0 + >; + }; + A55_COREGROUP_COST: coregroup-core0 { + busy-cost-data = < + 44 59 + 55 68 + 65 79 + 81 97 + 95 115 + 105 142 + 116 187 + 130 218 + 146 242 + 159 281 + 174 333 + 185 418 + 195 523 + >; + idle-cost-data = < + 14 + 14 + 0 + >; + }; + A75_COREGROUP_COST: coregroup-core1 { + busy-cost-data = < + 153 59 + 177 68 + 198 79 + 226 97 + 250 115 + 287 142 + 330 187 + 354 218 + 372 242 + 397 281 + 421 333 + 446 418 + 470 523 + >; + idle-cost-data = < + 14 + 14 + 0 + >; + }; + CH_COREGROUP_COST: coregroup-core2 { + busy-cost-data = < + 246 431 + 287 483 + 323 523 + 369 619 + 410 647 + 451 748 + 492 840 + 543 994 + 573 1150 + 614 1323 + 655 1530 + 717 1850 + 778 2205 + 819 2525 + 881 3325 + 922 4133 + 973 5150 + 1024 6335 + >; + idle-cost-data = < + 135 + 135 + 0 + >; + }; + DSU_CLUSTER_COST: cluster-core0 { + /* dummy energy table */ + busy-cost-data = < + 0 0 + >; + idle-cost-data = < + 0 + 0 + 0 + >; + }; + CH_CLUSTER_COST: cluster-core1 { + /* dummy energy table */ + busy-cost-data = < + 0 0 + >; + idle-cost-data = < + 0 + 0 + 0 + >; + }; + + }; + + ems { + /* Ontime Migration */ + ontime { + /* little cores */ + coregroup0 { + lower-boundary = <0>; + upper-boundary = <60>; + coverage-ratio = <100>; + }; + /* middle cores */ + coregroup1 { + lower-boundary = <25>; + upper-boundary = <75>; + coverage-ratio = <75>; + }; + /* big cores */ + coregroup2 { + lower-boundary = <35>; + upper-boundary = <100>; + coverage-ratio = <65>; + }; + }; + + /* Load Balance Trigger */ + #define DEFAULT_RATIO 80 + lbt { + overutil-level0 { + cpus = "0-3", + "4-5", + "6-7"; + ratio = <25>, + <25>, + <30>; + }; + overutil-level1 { + cpus = "0-5", + "6-7"; + ratio = <65>, + ; + }; + overutil-level2 { + cpus = "0-7"; + ratio = ; + }; + }; + }; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0xC4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xC4000003>; + }; + + cpupm { + #define POWERMODE_TYPE_CLUSTER 0 + #define POWERMODE_TYPE_SYSTEM 1 + + cpd_cl0 { + device_type = "cpupm"; + target-residency = <10000>; + psci-index = <128>; + type = ; + siblings = "0-5"; + }; + + cpd_cl1 { + device_type = "cpupm"; + target-residency = <10000>; + psci-index = <128>; + type = ; + siblings = "6-7"; + entry-allowed = "6-7"; + }; + + sicd { + device_type = "cpupm"; + target-residency = <10000>; /* us */ + psci-index = <256>; + type = ; + siblings = "0-7"; + entry-allowed = "0-5"; + system-idle; + }; + + vcpu_topology { + vcluster_cnt = <3>; + vcluster0_sibling = "0-3"; + vcluster1_sibling = "4-5"; + vcluster2_sibling = "6-7"; + }; + + idle-ip { + idle-ip-list = + "10510000.pwm", /* [ 0] pwm */ + "15c40000.adc", /* [ 1] adc */ + "10860000.hsi2c", /* [ 2] hsi2c_0 */ + "10870000.hsi2c", /* [ 3] hsi2c_1 */ + "10880000.hsi2c", /* [ 4] hsi2c_2 */ + "10890000.hsi2c", /* [ 5] hsi2c_3 */ + "10450000.hsi2c", /* [ 6] hsi2c_4 */ + "10460000.hsi2c", /* [ 7] hsi2c_5 */ + "10470000.hsi2c", /* [ 8] hsi2c_6 */ + "10480000.hsi2c", /* [ 9] hsi2c_7 */ + "10490000.hsi2c", /* [10] hsi2c_8 */ + "104a0000.hsi2c", /* [11] hsi2c_9 */ + "104b0000.hsi2c", /* [12] hsi2c_10 */ + "104c0000.hsi2c", /* [13] hsi2c_11 */ + "104d0000.hsi2c", /* [14] hsi2c_12 */ + "104e0000.hsi2c", /* [15] hsi2c_13 */ + "104f0000.hsi2c", /* [16] hsi2c_14 */ + "10500000.hsi2c", /* [17] hsi2c_15 */ + "108a0000.hsi2c", /* [18] hsi2c_16 */ + "108b0000.hsi2c", /* [19] hsi2c_17 */ + "108c0000.hsi2c", /* [20] hsi2c_18 */ + "108d0000.hsi2c", /* [21] hsi2c_19 */ + "108e0000.hsi2c", /* [22] hsi2c_20 */ + "108f0000.hsi2c", /* [23] hsi2c_21 */ + "10900000.hsi2c", /* [24] hsi2c_22 */ + "10910000.hsi2c", /* [25] hsi2c_23 */ + "10920000.hsi2c", /* [26] hsi2c_24 */ + "10930000.hsi2c", /* [27] hsi2c_25 */ + "10940000.hsi2c", /* [28] hsi2c_26 */ + "10950000.hsi2c", /* [29] hsi2c_27 */ + "10520000.hsi2c", /* [30] hsi2c_28 */ + "10530000.hsi2c", /* [31] hsi2c_29 */ + "10540000.hsi2c", /* [32] hsi2c_30 */ + "10550000.hsi2c", /* [33] hsi2c_31 */ + "10560000.hsi2c", /* [34] hsi2c_32 */ + "10570000.hsi2c", /* [35] hsi2c_33 */ + "10580000.hsi2c", /* [36] hsi2c_34 */ + "10590000.hsi2c", /* [37] hsi2c_35 */ + "10970000.hsi2c", /* [38] hsi2c_36 */ + "10990000.hsi2c", /* [39] hsi2c_37 */ + "109a0000.hsi2c", /* [40] hsi2c_38 */ + "15d00000.hsi2c", /* [41] hsi2c_39 */ + "15d10000.hsi2c", /* [42] hsi2c_40 */ + "15d20000.hsi2c", /* [43] hsi2c_41 */ + "15d30000.hsi2c", /* [44] hsi2c_42 */ + "15d40000.hsi2c", /* [45] hsi2c_43 */ + "15d50000.hsi2c", /* [46] hsi2c_44 */ + "15d60000.hsi2c", /* [47] hsi2c_45 */ + "15d70000.hsi2c", /* [48] hsi2c_46 */ + "10850000.spi", /* [49] spi_0 */ + "10450000.spi", /* [50] spi_1 */ + "10470000.spi", /* [51] spi_2 */ + "10490000.spi", /* [52] spi_3 */ + "104b0000.spi", /* [53] spi_4 */ + "104d0000.spi", /* [54] spi_5 */ + "104f0000.spi", /* [55] spi_6 */ + "108a0000.spi", /* [56] spi_7 */ + "108c0000.spi", /* [57] spi_8 */ + "108e0000.spi", /* [58] spi_9 */ + "10900000.spi", /* [59] spi_10 */ + "10920000.spi", /* [60] spi_11 */ + "10940000.spi", /* [61] spi_12 */ + "10520000.spi", /* [62] spi_13 */ + "10540000.spi", /* [63] spi_14 */ + "10560000.spi", /* [64] spi_15 */ + "10580000.spi", /* [65] spi_16 */ + "10970000.spi", /* [66] spi_17 */ + "10990000.spi", /* [67] spi_18 */ + "15d00000.spi", /* [68] spi_19 */ + "15d20000.spi", /* [69] spi_20 */ + "15d40000.spi", /* [70] spi_21 */ + "15d60000.spi", /* [71] spi_22 */ + "13d60000.ufs", /* [72] ufs */ + "10c00000.usb", /* [73] usb */ + "pd-aud", /* [74] pd-aud */ + "pd-dcf", /* [75] pd-dcf */ + "pd-dcpost", /* [76] pd-dcpost*/ + "pd-dcrd", /* [77] pd-dcrd */ + "pd-dpu", /* [78] pd-dpu */ + "pd-dspm", /* [79] pd-dspm */ + "pd-dsps", /* [80] pd-dsps */ + "pd-g2d", /* [81] pd-g2d */ + "pd-embedded_g3d", /* [82] pd-embedded_g3d */ + "pd-isppre", /* [83] pd-isppre*/ + "pd-isphq", /* [84] pd-isphq */ + "pd-isplp", /* [85] pd-isplp */ + "pd-iva", /* [86] pd-iva */ + "pd-mfc", /* [87] pd-mfc */ + "pd-vts", /* [88] pd-vts */ + "13ed0000.pcie0", /* [89] pcie0 */ + "13120000.pcie1", /* [90] pcie1 */ + "pd-vra2", /* [91] vra2 */ + "pd-npu0", /* [92] npu0 */ + "pd-npu1", /* [93] npu1 */ + "pd-fsys0a", /* [94] fsys0a */ + "13d00000.dwmmc2", /* [95] dwmmc2 */ + "130b0000.displayport"; /* [96] displayport */ + /* Append idle ip with ascending number from here + * Be advised that the end of entry must be with semicolon, not comma. + * and should be set in idle-ip-mask entry + */ + + /* to here idle ip */ + + fix-idle-ip = + "acpm_dvfs", + "dbg_core"; + fix-idle-ip-index = + <110>, + <111>; + + idle-ip-mask = + <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, + <10>, <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>, + <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>, <31>, <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>, + <40>, <41>, <42>, <43>, <44>, <45>, <46>, <47>, <48>, <49>, + <50>, <51>, <52>, <53>, <54>, <55>, <56>, <57>, <58>, <59>, + <60>, <61>, <62>, <63>, <64>, <65>, <66>, <67>, <68>, <69>, + <70>, <71>, <72>, <73>, <75>, <76>, <77>, <78>, <79>, + <80>, <81>, <82>, <83>, <84>, <85>, <86>, <87>, <89>, + <90>, <91>, <92>, <93>, <95>, <96>, + /* fix-idle-ip */ + <111>; + }; + }; + + exynos-pm { + compatible = "samsung,exynos-pm"; + reg = <0x0 0x15850000 0x1000>, + <0x0 0x10101200 0x100>; + reg-names = "gpio_alive_base", + "gicd_ispendrn_base"; + num-eint = <34>; + num-gic = <16>; + suspend_mode_idx = <8>; /* SYS_SLEEP */ + suspend_psci_idx = <1024>; /* PSCI_SYSTEM_SLEEP */ + cp_call_mode_idx = <10>; /* SYS_SLEEP_AUD_ON */ + cp_call_psci_idx = <1024>; /* PSCI_SYSTEM_SLEEP */ + + usbl2_suspend_available = <1>; /* SYS_SLEEP_USBL2 */ + usbl2_suspend_mode_idx = <12>; /* PSCI_SYSTEM_SLEEP */ + }; + + exynos-powermode { + wakeup-masks { + /* + * wakeup_mask configuration + * SICD SICD_CPD AFTR STOP + * LPD LPA ALPA DSTOP + * SLEEP SLEEP_VTS_ON SLEEP_AUD_ON FAPO + * USB_L2 + */ + wakeup-mask { + mask = <0x7ff81fff>, <0x0>, <0x0>, <0x0>, + <0x0>, <0x0>, <0x0>, <0x0>, + <0x1fef>, <0x1fef>, <0x1fef>, <0x0>, + <0x81fef>; + mask-offset = <0x3944>; + stat-offset = <0x3950>; + }; + }; + }; + + exynos-hiu { + compatible = "samsung,exynos-hiu"; + interrupts = <0 182 0>; // Hard Coding : INTREQ__CPUCL2_GCUIRQ + boot-freq = <1378000>; + boost-threshold = <1456000>; + boost-max = <2080000>; + sw-pbl = <0x36>; + bl1-inc = <0>; + bl2-inc = <0>; + bl3-inc = <0>; + tb-enabled; + operation-mode = <0>; + sibling-cpus = "6-7"; + /* PB BL PBL PWR_THR_INC */ + config-table = <0x1 0x2 0x48 0x0 /* config A */ + 0x1 0x3 0x60 0x0 /* config B */ + 0x0 0x1 0x36 0x0 /* config C */ + 0x1 0x2 0x48 0x0 /* config D */ + 0x1 0x3 0x60 0x0 /* config E */ + 0x0 0x1 0x36 0x0 /* config F */ + 0x1 0x2 0x48 0x0 /* config G */ + 0x1 0x3 0x60 0x0>; /* config H */ + }; + + exynos-ff { + device_type = "exynos-ff"; + boost-threshold = <1456000>; + sibling-cpus = "6-7"; + cal-id = ; + }; + + gic:interrupt-controller@10100000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x10101000 0x1000>, + <0x0 0x10102000 0x1000>, + <0x0 0x10104000 0x2000>, + <0x0 0x10106000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <26000000>; + use-clocksource-only; + use-physical-timer; + }; + + clock: clock-controller@0x1a240000 { + compatible = "samsung,exynos9820-clock"; + reg = <0x0 0x1a240000 0x8000>; + #clock-cells = <1>; + acpm-ipc-channel = <0>; + }; + cmu_ewf { + compatible = "samsung,exynos-cmuewf"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0x0 0x1A240000 0x1000>; + }; + + mct@10040000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x0 0x10040000 0x800>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, + <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>; + clocks = <&clock OSCCLK>, <&clock GATE_MCT>; + clock-names = "fin_pll", "mct"; + use-clockevent-only; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &gic 0 INTREQ__MCT_G0 0>, + <1 &gic 0 INTREQ__MCT_G1 0>, + <2 &gic 0 INTREQ__MCT_G2 0>, + <3 &gic 0 INTREQ__MCT_G3 0>, + <4 &gic 0 INTREQ__MCT_L0 0>, + <5 &gic 0 INTREQ__MCT_L1 0>, + <6 &gic 0 INTREQ__MCT_L2 0>, + <7 &gic 0 INTREQ__MCT_L3 0>, + <8 &gic 0 INTREQ__MCT_L4 0>, + <9 &gic 0 INTREQ__MCT_L5 0>, + <10 &gic 0 INTREQ__MCT_L6 0>, + <11 &gic 0 INTREQ__MCT_L7 0>; + }; + }; + + + ufs: ufs@0x13D60000 { + /* ----------------------- */ + /* 1. SYSTEM CONFIGURATION */ + /* ----------------------- */ + compatible ="samsung,exynos-ufs"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + reg = + <0x0 0x13D60000 0x200>, /* 0: HCI standard */ + <0x0 0x13D61100 0x200>, /* 1: Vendor specificed */ + <0x0 0x13D50000 0x8000>, /* 2: UNIPRO */ + <0x0 0x13D70000 0x100>; /* 3: UFS protector */ + interrupts = <0 INTREQ__UFS_EMBD 0>; + pinctrl-names = "default"; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + clocks = + /* aclk clock */ + <&clock GATE_UFS_EMBD>, + /* unipro clocks */ + <&clock UFS_EMBD>; + + clock-names = + /* aclk clocks */ + "GATE_UFS_EMBD", + /* unipro clocks */ + "UFS_EMBD"; + + /* PM QoS for INT power domain */ + ufs-pm-qos-int = <400000>; + + /* PM QoS for FSYS0 power domain */ + + + /* DMA coherent callback, should be coupled with 'ufs-sys' */ + dma-coherent; + + /* ----------------------- */ + /* 2. UFS COMMON */ + /* ----------------------- */ + freq-table-hz = <0 0>, <0 0>; + + vcc-supply = <&ufs_fixed_vcc>; + vcc-fixed-regulator; + + + /* ----------------------- */ + /* 3. UFS EXYNOS */ + /* ----------------------- */ + hw-rev = ; + + /* power mode change */ + ufs,pmd-attr-lane = /bits/ 8 <2>; + ufs,pmd-attr-gear = /bits/ 8 <3>; + + /* hiberantion */ + ufs-rx-min-activate-time-cap = <3>; + ufs-rx-hibern8-time-cap = <2>; + ufs-tx-hibern8-time-cap = <2>; + + /* board type for UFS CAL */ + brd-for-cal = <0>; + + fmp-id = <0>; + smu-id = <0>; + + /* ----------------------- */ + /* 4. ADDITIONAL NODES */ + /* ----------------------- */ + /* PHY isolation */ + ufs-phy { + #address-cells = <2>; + #size-cells = <1>; + ranges; + reg = <0x0 0x13D64000 0x800>; + }; + + /* SYSREG */ + ufs-io-coherency { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + reg = + <0x0 0x13C10700 0x4>; + + mask = <(BIT_22 | BIT_23)>; + bits = <(BIT_22 | BIT_23)>; + }; + + ufs-cport { + reg = + <0x0 0x13D68000 0x804>; + }; + }; + + ufs_fixed_vcc: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "ufs-vcc"; + gpio = <&gpd0 2 0>; + regulator-boot-on; + enable-active-high; + }; + + + /* ALIVE */ + pinctrl_0: pinctrl@15850000 { + compatible = "samsung,exynos9820-pinctrl"; + reg = <0x0 0x15850000 0x1000>; + interrupts = <0 INTREQ__ALIVE_EINT0 0>, <0 INTREQ__ALIVE_EINT1 0>, <0 INTREQ__ALIVE_EINT2 0>, + <0 INTREQ__ALIVE_EINT3 0>, <0 INTREQ__ALIVE_EINT4 0>, <0 INTREQ__ALIVE_EINT5 0>, + <0 INTREQ__ALIVE_EINT6 0>, <0 INTREQ__ALIVE_EINT7 0>, <0 INTREQ__ALIVE_EINT8 0>, + <0 INTREQ__ALIVE_EINT9 0>, <0 INTREQ__ALIVE_EINT10 0>, <0 INTREQ__ALIVE_EINT11 0>, + <0 INTREQ__ALIVE_EINT12 0>, <0 INTREQ__ALIVE_EINT13 0>, <0 INTREQ__ALIVE_EINT14 0>, + <0 INTREQ__ALIVE_EINT15 0>, <0 INTREQ__ALIVE_EINT16 0>, <0 INTREQ__ALIVE_EINT17 0>, + <0 INTREQ__ALIVE_EINT18 0>, <0 INTREQ__ALIVE_EINT19 0>, <0 INTREQ__ALIVE_EINT20 0>, + <0 INTREQ__ALIVE_EINT21 0>, <0 INTREQ__ALIVE_EINT22 0>, <0 INTREQ__ALIVE_EINT23 0>, + <0 INTREQ__ALIVE_EINT24 0>, <0 INTREQ__ALIVE_EINT25 0>, <0 INTREQ__ALIVE_EINT26 0>, + <0 INTREQ__ALIVE_EINT27 0>, <0 INTREQ__ALIVE_EINT28 0>, <0 INTREQ__ALIVE_EINT29 0>, + <0 INTREQ__ALIVE_EINT30 0>, <0 INTREQ__ALIVE_EINT31 0>, <0 INTREQ__ALIVE_EINT32 0>, + <0 INTREQ__ALIVE_EINT33 0>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + /* AUD */ + pinctrl_1: pinctrl@18C60000{ + compatible = "samsung,exynos9820-pinctrl"; + reg = <0x0 0x18C60000 0x1000>; + }; + + /* CMGP */ + pinctrl_2: pinctrl@15C30000{ + compatible = "samsung,exynos9820-pinctrl"; + reg = <0x0 0x15C30000 0x1000>; + interrupts = <0 INTREQ__EXT_INTM0_0 0>, <0 INTREQ__EXT_INTM0_1 0>, + <0 INTREQ__EXT_INTM0_2 0>, <0 INTREQ__EXT_INTM0_3 0>, + <0 INTREQ__EXT_INTM0_4 0>, <0 INTREQ__EXT_INTM0_5 0>, + <0 INTREQ__EXT_INTM0_6 0>, <0 INTREQ__EXT_INTM0_7 0>, + <0 INTREQ__EXT_INTM1_0 0>, <0 INTREQ__EXT_INTM1_1 0>, + <0 INTREQ__EXT_INTM1_2 0>, <0 INTREQ__EXT_INTM1_3 0>, + <0 INTREQ__EXT_INTM1_4 0>, <0 INTREQ__EXT_INTM1_5 0>, + <0 INTREQ__EXT_INTM1_6 0>, <0 INTREQ__EXT_INTM1_7 0>, + <0 INTREQ__EXT_INTM1_8 0>, <0 INTREQ__EXT_INTM1_9 0>, + <0 INTREQ__EXT_INTM2_0 0>, <0 INTREQ__EXT_INTM2_1 0>, + <0 INTREQ__EXT_INTM2_2 0>, <0 INTREQ__EXT_INTM2_3 0>, + <0 INTREQ__EXT_INTM2_4 0>, <0 INTREQ__EXT_INTM2_5 0>, + <0 INTREQ__EXT_INTM2_6 0>, <0 INTREQ__EXT_INTM2_7 0>, + <0 INTREQ__EXT_INTM2_8 0>, <0 INTREQ__EXT_INTM2_9 0>, + <0 INTREQ__EXT_INTM3_0 0>, <0 INTREQ__EXT_INTM3_1 0>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + /* FSYS0 */ + pinctrl_3: pinctrl@13030000 { + compatible = "samsung,exynos9820-pinctrl"; + reg = <0x0 0x13030000 0x1000>; + interrupts = <0 INTREQ__GPIO_FSYS0 0>; + }; + + /* FSYS1 */ + pinctrl_4: pinctrl@13C40000 { + compatible = "samsung,exynos9820-pinctrl"; + reg = <0x0 0x13C40000 0x1000>; + interrupts = <0 INTREQ__GPIO_FSYS1 0>; + }; + + /* PERIC0 */ + pinctrl_5: pinctrl@10430000 { + compatible = "samsung,exynos9820-pinctrl"; + reg = <0x0 0x10430000 0x1000>; + interrupts = <0 INTREQ__GPIO_PERIC0 0>; + }; + + /* PERIC1 */ + pinctrl_6: pinctrl@10830000 { + compatible = "samsung,exynos9820-pinctrl"; + reg = <0x0 0x10830000 0x1000>; + interrupts = <0 INTREQ__GPIO_PERIC1 0>; + }; +#if 1 + /* VTS */ + pinctrl_7: pinctrl@15580000 { + compatible = "samsung,exynos9820-pinctrl"; + reg = <0x0 0x15580000 0x1000>; + }; +#endif + + exynos_flexpmu_dbg { + compatible = "samsung,exynos-flexpmu-dbg"; + #address-cells = <2>; + #size-cells = <1>; + data-base = <0x204bc00>; + data-size = <0x400>; + }; + + exynos-ocp { + compatible = "samsung,exynos-ocp"; + + interrupts = <0 INTREQ__CPUCL2_GCUIRQ 0>; + + sibling-cpus = "6-7"; + down-step = <1>; + + max-freq-wo-ocp = <1820000>; + + release-mode = <1>; /* 0 : current meter, 1 : cpu utilization */ + release-threshold = <50>; /* @current meter : current(A), @cpu load : capacity ratio(%) */ + release-duration = <15>; /* msec */ + }; + + exynos-pmu { + compatible = "samsung,exynos-pmu"; + samsung,syscon-phandle = <&pmu_system_controller>; + reg = <0x0 0x15860000 0x10000>; + reg-names = "pmu_alive"; + }; + + pmu_system_controller: system-controller@15860000 { + compatible = "samsung,exynos9820-pmu", "syscon"; + reg = <0x0 0x15860000 0x10000>; + }; + + vbat: vbat { + compatible = "regulator-fixed"; + regulator-name = "VBAT"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-boot-on; + }; + + abox_gic: abox-gic@18cf0000 { + compatible = "samsung,abox-gic"; + reg = <0x0 0x18cf1000 0x1000>, <0x0 0x18cf2000 0x1004>; + reg-names = "gicd", "gicc"; + interrupts = <0 INTREQ__AUD_ABOX_GIC400 0>; + }; + + abox: abox@18c50000 { + compatible = "samsung,abox"; + reg = <0x0 0x18c50000 0x10000>, <0x0 0x18c10000 0x10000>, + <0x0 0x18d00000 0x59000>, <0x0 0x18ce0000 0x10000>; + reg-names = "sfr", "sysreg", "sram", "timer"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + samsung,quirks = "try to asrc off"; + #sound-dai-cells = <1>; + samsung,ipc-tx-offset = <0x2f000>; + samsung,ipc-rx-offset = <0x2f300>; + samsung,ipc-tx-ack-offset = <0x2f2fc>; + samsung,ipc-rx-ack-offset = <0x2f5fc>; + samsung,ipc-tx-area = <0x1 0x850000 0x4000>; + samsung,ipc-rx-area = <0x1 0x854000 0x4000>; + samsung,abox-gic = <&abox_gic>; + clocks = <&clock PLL_OUT_AUD0>, <&clock PLL_OUT_AUD1>, <&clock DOUT_CLK_AUD_AUDIF>, + <&clock DOUT_CLK_AUD_DMIC>, <&clock DOUT_CLK_AUD_BUS>, <&clock DOUT_CLK_AUD_CNT>; + clock-names = "pll", "pll1", "audif", "dmic", "bus", "cnt"; + samsung,uaif-max-div = <512>; + iommus = <&sysmmu_aud>; + samsung,pm-qos-int = <0 0 0 0 0>; + samsung,pm-qos-aud = <1180000 800000 590000 394000 0>; + + abox_core0: abox-core@18c55000 { + compatible = "samsung,abox-core"; + reg = <0x0 0x18c55000 0x80>, <0x0 0x18c55100 0x4>; + reg-names = "gpr", "status"; + samsung,id = <0>; + samsung,type = "CA32"; + samsung,pmu_power = <0x2d80 0x1>; + samsung,pmu_enable = <0x2da0 0x1>; + samsung,pmu_standby = <0x2da4 0x11>; + abox_firmware_sram0: abox-firmware-sram0 { + samsung,name = "calliope_sram.bin"; + samsung,area = <0>; /* 0:SRAM, 1:DRAM */ + samsung,offset = <0x0>; + }; + abox_firmware_dram0: abox-firmware-dram0 { + samsung,name = "calliope_dram.bin"; + samsung,area = <1>; /* 0:SRAM, 1:DRAM */ + samsung,offset = <0x0>; + }; + }; + + abox_core1: abox-core@18c55080 { + compatible = "samsung,abox-core"; + reg = <0x0 0x18c55080 0x80>, <0x0 0x18c55100 0x4>; + reg-names = "gpr", "status"; + samsung,id = <1>; + samsung,type = "CA32"; + samsung,pmu_power = <0x2e00 0x1>; + samsung,pmu_enable = <0x2e20 0x1>; + samsung,pmu_standby = <0x2e24 0x1>; + abox_firmware_sram1: abox-firmware-sram1 { + samsung,name = "calliope_sram_2.bin"; + samsung,area = <0>; /* 0:SRAM, 1:DRAM */ + samsung,offset = <0x32000>; + }; + abox_firmware_dram1: abox-firmware-dram1 { + samsung,name = "calliope_dram_2.bin"; + samsung,area = <1>; /* 0:SRAM, 1:DRAM */ + samsung,offset = <0x280000>; + }; + }; + + abox_rdma_0: abox-rdma@18c51000 { + compatible = "samsung,abox-rdma"; + reg = <0x0 0x18c51000 0x100>; + reg-names = "sfr"; + samsung,id = <0>; + samsung,type = "normal"; + #sound-dai-cells = <0>; + }; + + abox_rdma_1: abox-rdma@18c51100 { + compatible = "samsung,abox-rdma"; + reg = <0x0 0x18c51100 0x100>; + reg-names = "sfr"; + samsung,id = <1>; + samsung,type = "normal"; + #sound-dai-cells = <0>; + }; + + abox_rdma_2: abox-rdma@18c51200 { + compatible = "samsung,abox-rdma"; + reg = <0x0 0x18c51200 0x100>; + reg-names = "sfr"; + samsung,id = <2>; + samsung,type = "normal"; + #sound-dai-cells = <0>; + }; + + abox_rdma_3: abox-rdma@18c51300 { + compatible = "samsung,abox-rdma"; + reg = <0x0 0x18c51300 0x100>; + reg-names = "sfr"; + samsung,id = <3>; + samsung,type = "sync"; + #sound-dai-cells = <0>; + }; + + abox_rdma_4: abox-rdma@18c51400 { + compatible = "samsung,abox-rdma"; + reg = <0x0 0x18c51400 0x100>; + reg-names = "sfr"; + samsung,id = <4>; + samsung,type = "call"; + #sound-dai-cells = <0>; + }; + + abox_rdma_5: abox-rdma@18c51500 { + compatible = "samsung,abox-rdma"; + reg = <0x0 0x18c51500 0x100>, <0x0 0x18d2f600 0x70>; + reg-names = "sfr", "mailbox"; + samsung,id = <5>; + samsung,type = "compress"; + #sound-dai-cells = <0>; + }; + + abox_rdma_6: abox-rdma@18c51600 { + compatible = "samsung,abox-rdma"; + reg = <0x0 0x18c51600 0x100>; + reg-names = "sfr"; + samsung,id = <6>; + samsung,type = "realtime"; + #sound-dai-cells = <0>; + }; + + abox_rdma_7: abox-rdma@18c51700 { + compatible = "samsung,abox-rdma"; + reg = <0x0 0x18c51700 0x100>; + reg-names = "sfr"; + samsung,id = <7>; + samsung,type = "realtime"; + #sound-dai-cells = <0>; + }; + + abox_rdma_8: abox-rdma@18c51800 { + compatible = "samsung,abox-rdma"; + reg = <0x0 0x18c51800 0x100>; + reg-names = "sfr"; + samsung,id = <8>; + samsung,type = "normal"; + #sound-dai-cells = <0>; + }; + + abox_rdma_9: abox-rdma@18c51900 { + compatible = "samsung,abox-rdma"; + reg = <0x0 0x18c51900 0x100>; + reg-names = "sfr"; + samsung,id = <9>; + samsung,type = "normal"; + #sound-dai-cells = <0>; + }; + + abox_rdma_10: abox-rdma@18c51a00 { + compatible = "samsung,abox-rdma"; + reg = <0x0 0x18c51a00 0x100>; + reg-names = "sfr"; + samsung,id = <10>; + samsung,type = "normal"; + #sound-dai-cells = <0>; + }; + + abox_rdma_11: abox-rdma@18c51b00 { + compatible = "samsung,abox-rdma"; + reg = <0x0 0x18c51b00 0x100>; + reg-names = "sfr"; + samsung,id = <11>; + samsung,type = "normal"; + #sound-dai-cells = <0>; + }; + + abox_wdma_0: abox-wdma@18c53000 { + compatible = "samsung,abox-wdma"; + reg = <0x0 0x18c53000 0x100>; + reg-names = "sfr"; + samsung,id = <0>; + samsung,type = "realtime"; + #sound-dai-cells = <0>; + }; + + abox_wdma_1: abox-wdma@18c53100 { + compatible = "samsung,abox-wdma"; + reg = <0x0 0x18c53100 0x100>; + reg-names = "sfr"; + samsung,id = <1>; + samsung,type = "normal"; + #sound-dai-cells = <0>; + }; + + abox_wdma_2: abox-wdma@18c53200 { + compatible = "samsung,abox-wdma"; + reg = <0x0 0x18c53200 0x100>; + reg-names = "sfr"; + samsung,id = <2>; + samsung,type = "call"; + #sound-dai-cells = <0>; + }; + + abox_wdma_3: abox-wdma@18c53300 { + compatible = "samsung,abox-wdma"; + reg = <0x0 0x18c53300 0x100>; + reg-names = "sfr"; + samsung,id = <3>; + samsung,type = "realtime"; + #sound-dai-cells = <0>; + }; + + abox_wdma_4: abox-wdma@18c53400 { + compatible = "samsung,abox-wdma"; + reg = <0x0 0x18c53400 0x100>; + reg-names = "sfr"; + samsung,id = <4>; + samsung,type = "vi-sensing"; + #sound-dai-cells = <0>; + }; + + abox_wdma_5: abox-wdma@18c53500 { + compatible = "samsung,abox-wdma"; + reg = <0x0 0x18c53500 0x100>; + reg-names = "sfr"; + samsung,id = <5>; + samsung,type = "normal"; + #sound-dai-cells = <0>; + }; + + abox_wdma_6: abox-wdma@18c53600 { + compatible = "samsung,abox-wdma"; + reg = <0x0 0x18c53600 0x100>; + reg-names = "sfr"; + samsung,id = <6>; + samsung,type = "normal"; + #sound-dai-cells = <0>; + }; + + abox_wdma_7: abox-wdma@18c53700 { + compatible = "samsung,abox-wdma"; + reg = <0x0 0x18c53700 0x100>; + reg-names = "sfr"; + samsung,id = <7>; + samsung,type = "normal"; + #sound-dai-cells = <0>; + }; + + abox_uaif_0: abox-uaif@18c50500 { + compatible = "samsung,abox-uaif"; + reg = <0x0 0x18c50500 0x10>; + reg-names = "sfr"; + id = <0>; + clocks = <&clock DOUT_CLK_AUD_UAIF0>, <&clock GATE_ABOX_BCLK0>; + clock-names = "bclk", "bclk_gate"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&aud_i2s0_bus>; + pinctrl-1 = <&aud_i2s0_idle>; + #sound-dai-cells = <0>; + }; + + abox_uaif_1: abox-uaif@18c50510 { + compatible = "samsung,abox-uaif"; + reg = <0x0 0x18c50510 0x10>; + reg-names = "sfr"; + id = <1>; + clocks = <&clock DOUT_CLK_AUD_UAIF1>, <&clock GATE_ABOX_BCLK1>; + clock-names = "bclk", "bclk_gate"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&aud_i2s1_bus>; + pinctrl-1 = <&aud_i2s1_idle>; + #sound-dai-cells = <0>; + }; + + abox_uaif_2: abox-uaif@18c50520 { + compatible = "samsung,abox-uaif"; + reg = <0x0 0x18c50520 0x10>; + reg-names = "sfr"; + id = <2>; + clocks = <&clock DOUT_CLK_AUD_UAIF2>, <&clock GATE_ABOX_BCLK2>; + clock-names = "bclk", "bclk_gate"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&aud_i2s2_bus>; + pinctrl-1 = <&aud_i2s2_idle>; + #sound-dai-cells = <0>; + }; + + abox_uaif_3: abox-uaif@18c50530 { + compatible = "samsung,abox-uaif"; + reg = <0x0 0x18c50530 0x10>; + reg-names = "sfr"; + id = <3>; + clocks = <&clock DOUT_CLK_AUD_UAIF3>, <&clock GATE_ABOX_BCLK3>; + clock-names = "bclk", "bclk_gate"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&aud_i2s3_bus>; + pinctrl-1 = <&aud_i2s3_idle>; + #sound-dai-cells = <0>; + }; + + abox_dsif: abox-dsif@18c50550 { + compatible = "samsung,abox-dsif"; + reg = <0x0 0x18c50550 0x10>; + reg-names = "sfr"; + id = <5>; + clocks = <&clock DOUT_CLK_AUD_DSIF>, <&clock GATE_ABOX_BCLK_DSIF>; + clock-names = "bclk", "bclk_gate"; + /* DSIF and UAIF2 shares GPIO + * pinctrl-names = "default", "sleep"; + * pinctrl-0 = <&aud_dsd_bus>; + * pinctrl-1 = <&aud_dsd_idle>; + */ + #sound-dai-cells = <0>; + }; + + abox_effect: abox-effect@18d2e000 { + compatible = "samsung,abox-effect"; + reg = <0x0 0x18d2e000 0x1000>; + reg-names = "reg"; + }; + + abox_debug: abox-debug@0 { + compatible = "samsung,abox-debug"; + memory-region = <&abox_rmem>; + reg = <0x0 0x0 0x0>; + }; + + abox_vss: abox-vss@0 { + compatible = "samsung,abox-vss"; + samsung,magic-offset = <0x700000>; + reg = <0x0 0x0 0x0>; + }; + + ext_bin_0: ext-bin@0 { + status = "okay"; + samsung,name = "dsm.bin"; + samsung,area = <1>; /* 0:SRAM, 1:DRAM, 2:VSS */ + samsung,offset = <0x502000>; + }; + ext_bin_1: ext-bin@1 { + status = "okay"; + samsung,name = "AP_AUDIO_SLSI.bin"; + samsung,area = <1>; + samsung,offset = <0x7f0000>; + }; + ext_bin_2: ext-bin@2 { + status = "okay"; + samsung,name = "APBargeIn_AUDIO_SLSI.bin"; + samsung,area = <1>; + samsung,offset = <0x7ec000>; + }; + ext_bin_3: ext-bin@3 { + status = "disabled"; + samsung,name = "SoundBoosterParam.bin"; + samsung,area = <1>; + samsung,offset = <0x4fc000>; + }; + ext_bin_4: ext-bin@4 { + status = "okay"; + samsung,name = "APDV_AUDIO_SLSI.bin"; + samsung,area = <1>; + samsung,offset = <0x4d0000>; + }; + ext_bin_5: ext-bin@5 { + status = "okay"; + samsung,name = "APBiBF_AUDIO_SLSI.bin"; + samsung,area = <1>; + samsung,offset = <0x7ef000>; + }; + ext_bin_6: ext-bin@6 { + status = "disabled"; + samsung,name = "dummy.bin"; + samsung,area = <1>; + samsung,offset = <0x800000>; + }; + ext_bin_7: ext-bin@7 { + status = "okay"; + samsung,name = "usbout.bin"; + samsung,area = <1>; + samsung,offset = <0x1100000>; + }; + ext_bin_8: ext-bin@8 { + status = "okay"; + samsung,name = "usbin.bin"; + samsung,area = <1>; + samsung,offset = <0x1110000>; + }; + ext_bin_9: ext-bin@9 { + status = "okay"; + samsung,name = "btsco.bin"; + samsung,area = <1>; + samsung,offset = <0x1180000>; + }; + ext_bin_10: ext-bin@a { + status = "okay"; + samsung,name = "fmradio.bin"; + samsung,area = <1>; + samsung,offset = <0x1188000>; + }; + ext_bin_11: ext-bin@b { + status = "okay"; + samsung,name = "rxse1.bin"; + samsung,area = <1>; + samsung,offset = <0x1190000>; + }; + ext_bin_12: ext-bin@c { + status = "okay"; + samsung,name = "txse1.bin"; + samsung,area = <1>; + samsung,offset = <0x1198000>; + }; + ext_bin_13: ext-bin@d { + status = "okay"; + samsung,name = "txse2.bin"; + samsung,area = <1>; + samsung,offset = <0x11a0000>; + }; + ext_bin_14: ext-bin@e { + status = "okay"; + samsung,name = "vmcalliope"; + samsung,area = <1>; + samsung,offset = <0x11a8000>; + }; + ext_bin_15: ext-bin@f { + status = "okay"; + samsung,name = "calliope2.dt"; + samsung,area = <1>; + samsung,offset = <0x11fe000>; + samsung,mixer-control; + }; + }; + + iommu-domain_dpu { + compatible = "samsung,exynos-iommu-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + domain-clients = <&dsim_0>, <&displayport>; + }; + + dpp_0: dpp@0x19071000 { /* GF0 */ + compatible = "samsung,exynos9-dpp"; + #pb-id-cells = <3>; + /* DPU_DMA, DPP, DPU_DMA_COMMON */ + reg = <0x0 0x19071000 0x1000>, <0x0 0x19021000 0x1000>, <0x0 0x19070000 0x110>; + /* DPU_DMA IRQ, DPP IRQ */ + interrupts = <0 INTREQ__DPU_DMA_GF0 0>, <0 INTREQ__DPU_DPP_GF0 0>; + /* Each bit indicates DPP attribute */ + /* 0:AFBC 1:BLOCK 2:FLIP 3:ROT 4:CSC 5:SCALE 6:HDR 7:HDR10 */ + /* 16:IDMA 17:ODMA 18:DPP */ + attr = <0x50087>; /* DPP/IDMA/HDR10/FLIP/BLOCK/AFBC */ + port = <0>; /* AXI port number */ + + /* HW restriction */ + src_f_w = <16 65534 1>; + src_f_h = <16 8190 1>; + src_w = <16 4096 1>; + src_h = <16 4096 1>; + src_xy_align = <1 1>; + + dst_f_w = <16 8190 1>; + dst_f_h = <16 8190 1>; + dst_w = <16 4096 1>; + dst_h = <16 4096 1>; + dst_xy_align = <1 1>; + + blk_w = <4 4096 1>; + blk_h = <1 4096 1>; + blk_xy_align = <1 1>; + + src_h_rot_max = <2160>; + }; + + dpp_1: dpp@0x19076000 { /* VGRFS */ + compatible = "samsung,exynos9-dpp"; + #pb-id-cells = <3>; + reg = <0x0 0x19076000 0x1000>, <0x0 0x19026000 0x1000>; + interrupts = <0 INTREQ__DPU_DMA_VGRFS 0>, <0 INTREQ__DPU_DPP_VGRFS 0>; + attr = <0x500FF>; /* DPP/IDMA/HDR10/HDR/SCALE/CSC/FLIP/BLOCK/AFBC */ + port = <0>; + }; + + dpp_2: dpp@0x19072000 { /* GF1 */ + compatible = "samsung,exynos9-dpp"; + #pb-id-cells = <3>; + reg = <0x0 0x19072000 0x1000>, <0x0 0x19022000 0x1000>; + interrupts = <0 INTREQ__DPU_DMA_GF1 0>, <0 INTREQ__DPU_DPP_GF1 0>; + attr = <0x50087>; /* DPP/IDMA/HDR10/FLIP/BLOCK/AFBC */ + port = <1>; + }; + + dpp_3: dpp@0x19075000 { /* VGF */ + compatible = "samsung,exynos9-dpp"; + #pb-id-cells = <3>; + reg = <0x0 0x19075000 0x1000>, <0x0 0x19024000 0x1000>; + interrupts = <0 INTREQ__DPU_DMA_VGF 0>, <0 INTREQ__DPU_DPP_VGF 0>; + attr = <0x50097>; /* DPP/IDMA/HDR10/CSC/FLIP/BLOCK/AFBC */ + port = <1>; + }; + + dpp_4: dpp@0x19073000 { /* VG */ + compatible = "samsung,exynos9-dpp"; + #pb-id-cells = <3>; + reg = <0x0 0x19073000 0x1000>, <0x0 0x19023000 0x1000>; + interrupts = <0 INTREQ__DPU_DMA_VG 0>, <0 INTREQ__DPU_DPP_VG 0>; + attr = <0x50096>; /* DPP/IDMA/HDR10/CSC/FLIP/BLOCK */ + port = <2>; + }; + + dpp_5: dpp@0x19074000 { /* VGS */ + compatible = "samsung,exynos9-dpp"; + #pb-id-cells = <3>; + reg = <0x0 0x19074000 0x1000>, <0x0 0x19025000 0x1000>; + interrupts = <0 INTREQ__DPU_DMA_VGS 0>, <0 INTREQ__DPU_DPP_VGS 0>; + attr = <0x500B6>; /* DPP/IDMA/HDR10/SCALE/CSC/FLIP/BLOCK */ + port = <2>; + }; + + disp_ss: disp_ss@0x16010000 { + compatible = "samsung,exynos9-disp_ss"; + reg = <0x0 0x19011000 0x10>; + }; + + fmp_0: fmp { + compatible = "samsung,exynos-fmp"; + }; + + mipi_phy_dsim0_m4s4_top: dphy_m4s4_dsim0@0x19160000 { + compatible = "samsung,mipi-phy-m4s4-top"; + isolation = <0x070c>; + owner = <0>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_dsim0_m4s0: dphy_m4s0_dsim0@0x19161000 { + compatible = "samsung,mipi-phy-m4s0"; + isolation = <0x0710>; + owner = <0>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + dsim_0: dsim@0x19080000 { + compatible = "samsung,exynos9-dsim"; + reg = <0x0 0x19080000 0x300>, <0x0 0x19161000 0x800>, <0x0 0x19160000 0x100>; + interrupts = <0 INTREQ__DPU_DSIM0 0>; + iommus = <&sysmmu_dpu0>, <&sysmmu_dpu1>, <&sysmmu_dpu2>; + + /* clock */ + clock-names = "aclk"; + clocks = <&clock GATE_DPU_DPU>; + + phys = <&mipi_phy_dsim0_m4s0 0>, <&mipi_phy_dsim0_m4s4_top 0>; + phy-names = "dsim_dphy", "dsim_dphy_extra"; + }; + + displayport: displayport@0x130B0000 { + compatible = "samsung,exynos-displayport"; + reg = <0x0 0x130B0000 0xFFFF>, + <0x0 0x10AE0000 0x20CC>; + interrupts = <0 INTREQ__DP_LINK 0>; + iommus = <&sysmmu_dpu0>, <&sysmmu_dpu1>, <&sysmmu_dpu2>; + + /* clock */ + clock-names = "aclk"; + clocks = <&clock GATE_DPU_DPU>; + }; + + decon_f: decon_f@0x19030000 { + compatible = "samsung,exynos9-decon"; + #pb-id-cells = <4>; + reg = <0x0 0x19030000 0x10000>; + + /* interrupt num : FRAME_START, FRMAE_DONE, EXTRA, GPIO_PERIC1(EXT_INT_TE: GPD0[0]) */ + interrupts = <0 INTREQ__DPU_DECON0_FRAME_START 0>, + <0 INTREQ__DPU_DECON0_FRAME_DONE 0>, + <0 INTREQ__DPU_DECON0_EXTRA 0>, + <0 INTREQ__GPIO_PERIC1 0>; + + /* pinctrl */ + pinctrl-names = "hw_te_on", "hw_te_off"; + pinctrl-0 = <&decon_f_te_on>; + pinctrl-1 = <&decon_f_te_off>; + + max_win = <6>; + default_win = <5>; + default_idma = <0>; + psr_mode = <2>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */ + trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */ + dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */ + + /* 0: DSI, 1: eDP, 2:HDMI, 3: WB */ + out_type = <0>; + /* 0: DSI0, 1: DSI1, 2: DSI2 */ + out_idx = <0>; + + /* pixel per clock */ + ppc = <2>; + + chip_ver = <9820>; + + dpp_cnt = <7>; + dsim_cnt = <2>; + decon_cnt = <3>; + + #address-cells = <2>; + #size-cells = <1>; + ranges; + + /* EINT for TE */ + gpios = <&gpd0 0 0xf>; + /* sw te pending register */ + te_eint { + /* NWEINT_GPD0_PEND */ + reg = <0x0 0x10830a14 0x4>; + }; + + cam-stat { + /* ISPPRE_STATUS(0x15862504) */ + reg = <0x0 0x15862504 0x4>; + }; + }; + + decon_t: decon_t@0x19050000 { + compatible = "samsung,exynos9-decon"; /* exynos9820 */ + #pb-id-cells = <4>; + reg = <0x0 0x19050000 0x10000>; + + /* interrupt num : FRAME_START, FRMAE_DONE, EXTRA */ + interrupts = <0 INTREQ__DPU_DECON2_FRAME_START 0>, + <0 INTREQ__DPU_DECON2_FRAME_DONE 0>, + <0 INTREQ__DPU_DECON2_EXTRA 0>; + + max_win = <6>; + default_win = <4>; + default_idma = <1>; + psr_mode = <0>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */ + trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */ + dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */ + + /* 0: DSI, 1: eDP, 2:DP */ + out_type = <2>; + /* 0: DSI0, 1: DSI1, 2: DSI2 */ + out_idx = <0>; + + /* pixel per clock */ + ppc = <2>; + + dpp_cnt = <7>; + dsim_cnt = <2>; + decon_cnt = <3>; + + #address-cells = <2>; + #size-cells = <1>; + ranges; + }; + + acpm { + compatible = "samsung,exynos-acpm"; + #address-cells = <2>; + #size-cells = <1>; + acpm-ipc-channel = <4>; + fvmap_offset = <0xA400>; + reg = <0x0 0x15830000 0x1000>; /* TIMER_APM */ + reg-names = "timer_apm"; + peritimer-cnt = <0xFFFF>; + }; + + acpm_ipc { + compatible = "samsung,exynos-acpm-ipc"; + #address-cells = <2>; + #size-cells = <1>; + interrupts = <0 INTREQ__MAILBOX_APM2AP 0>; /* AP2APM MAILBOX SPI NUM*/ + reg = <0x0 0x15900000 0x1000>, /* AP2APM MAILBOX */ + <0x0 0x2039000 0x30000>; /* APM SRAM */ + initdata-base = <0x7000>; + num-timestamps = <32>; + debug-log-level = <0>; + logging-period = <500>; + dump-base = <0x203C000>; + dump-size = <0x2D000>; /* 180KB */ + }; + + acpm_dvfs { + compatible = "samsung,exynos-acpm-dvfs"; + acpm-ipc-channel = <5>; + }; + + /* DMA */ + amba { + #address-cells = <2>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma0@1A2E0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x1A2E0000 0x1000>; + interrupts = <0 INTREQ__PDMA0 0>; + clocks = <&clock GATE_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + #dma-multi-irq = <1>; + dma-arwrapper = <0x1A2E4400>, + <0x1A2E4420>, + <0x1A2E4440>, + <0x1A2E4460>, + <0x1A2E4480>, + <0x1A2E44A0>, + <0x1A2E44C0>, + <0x1A2E44E0>; + dma-awwrapper = <0x1A2E4404>, + <0x1A2E4424>, + <0x1A2E4444>, + <0x1A2E4464>, + <0x1A2E4484>, + <0x1A2E44A4>, + <0x1A2E44C4>, + <0x1A2E44E4>; + dma-instwrapper = <0x1A2E4500>; + dma-mask-bit = <36>; + coherent-mask-bit = <36>; + }; + }; + + /* mali */ + mali: mali@18500000 { + compatible = "arm,mali"; + reg = <0x0 0x18500000 0x5000>; + interrupts = <0 288 0>, + <0 287 0>, + <0 289 0>; + interrupt-names = "JOB", "MMU", "GPU"; + g3d_cmu_cal_id = ; + samsung,power-domain = <&pd_embedded_g3d>; + #cooling-cells = <2>; /* min followed by max */ + governor = "dynamic"; + interactive_info = <455 94 0>; + gpu_dvfs_table_size = <8 8>; /**/ + /* 8 columns freq down up stay mif little middle big */ + gpu_dvfs_table = < 676 93 100 9 2093000 1742000 1586000 0 + 650 90 97 9 2093000 1742000 1586000 0 + 598 88 97 9 1794000 1742000 1586000 0 + 572 80 92 5 1794000 1742000 1586000 0 + 546 65 83 1 1539000 1586000 1508000 0 + 455 53 78 1 1352000 1300000 1404000 0 + 325 64 74 1 1014000 0 0 0 + 260 0 80 1 676000 0 0 0 >; + gpu_pmqos_cpu_cluster_num = <3>; + gpu_pmu_status_reg_offset = <0x2104>; + gpu_pmu_status_local_pwr_mask = <0x1>; /*0x1 << 0*/ + gpu_max_clock = <676>; + gpu_max_clock_limit = <676>; + gpu_min_clock = <260>; + gpu_dvfs_start_clock = <260>; + gpu_dvfs_bl_config_clock = <260>; + gpu_default_voltage = <800000>; + gpu_cold_minimum_vol = <0>; + gpu_voltage_offset_margin = <37500>; + gpu_tmu_control = <1>; + gpu_temp_throttling_level_num = <6>; + gpu_temp_throttling = <676 546 455 325 260 260>; + gpu_power_coeff = <625>; + gpu_dvfs_time_interval = <5>; /*1 tick : 10ms*/ + gpu_default_wakeup_lock = <1>; + gpu_bus_devfreq = <1>; + gpu_dynamic_abb = <0>; + gpu_early_clk_gating = <0>; + gpu_dvs = <0>; + gpu_inter_frame_pm = <1>; + gpu_perf_gathering = <0>; + gpu_runtime_pm_delay_time = <50>; + gpu_dvfs_polling_time = <30>; + gpu_pmqos_int_disable = <1>; + gpu_pmqos_mif_max_clock = <2093000>; + gpu_pmqos_mif_max_clock_base = <676>; + gpu_cl_dvfs_start_base = <455>; + gpu_debug_level = <3>; /*DEBUG(1) INFO(2) WARNING(3) ERROR(4)*/ + gpu_trace_level = <8>; /*TRACE_ALL*/ + gpu_mo_min_clock = <455>; + gpu_boost_gpu_min_lock = <0>; + gpu_boost_egl_min_lock = <1872000>; + gpu_vk_boost_max_lock = <338>; + gpu_vk_boost_mif_min_lock = <1794000>; + }; + + + /* USI_00 */ + usi_0: usi@10421004 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421004 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_00_I2C */ + usi_0_i2c: usi@10421008 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421008 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_01 */ + usi_1: usi@1042100c { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x1042100c 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_01_I2C */ + usi_1_i2c: usi@10421010 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421010 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_02 */ + usi_2: usi@10421014 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421014 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_02_I2C */ + usi_2_i2c: usi@10421018 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421018 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_03 */ + usi_3: usi@1042101C { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x1042101c 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_03_I2C */ + usi_3_i2c: usi@10421020 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421020 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_04 */ + usi_4: usi@10421024 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421024 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_04_I2C */ + usi_4_i2c: usi@10421028 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421028 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_05 */ + usi_5: usi@1042102C { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x1042102C 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_05_I2C */ + usi_5_i2c: usi@10421030 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421030 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_06 */ + usi_6: usi@10821018 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821018 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_06_I2C */ + usi_6_i2c: usi@1082101C { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x1082101C 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_07 */ + usi_7: usi@10821020 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821020 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_07_I2C */ + usi_7_i2c: usi@10821024 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821024 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_08 */ + usi_8: usi@10821028 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821028 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_08_I2C */ + usi_8_i2c: usi@1082102C { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x1082102C 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_09 */ + usi_9: usi@10821030 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821030 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_09_I2C */ + usi_9_i2c: usi@10821034 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821034 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_10 */ + usi_10: usi@10821038 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821038 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_10_I2C */ + usi_10_i2c: usi@1082103C { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x1082103C 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_11 */ + usi_11: usi@10821040 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821040 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_11_I2C */ + usi_11_i2c: usi@10821044 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821044 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_12 */ + usi_12: usi@10421034 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421034 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_12_I2C */ + usi_12_i2c: usi@10421038 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421038 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_13 */ + usi_13: usi@1042103C { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x1042103C 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_13_I2C */ + usi_13_i2c: usi@10421040 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421040 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_14 */ + usi_14: usi@10421044 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421044 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_14_I2C */ + usi_14_i2c: usi@10421048 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421048 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_15 */ + usi_15: usi@1042104C { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x1042104C 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_15_I2C */ + usi_15_i2c: usi@10421050 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421050 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_16 */ + usi_16: usi@10821048 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821048 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_17 */ + usi_17: usi@1082104C { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x1082104C 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_17_I2C */ + usi_17_i2c: usi@10821050 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821050 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_00_CMGP */ + usi_00_cmgp: usi@15C22000 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x15C22000 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_00_CMGP_I2C */ + usi_00_cmgp_i2c: usi@15C22004 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x15C22004 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_01_CMGP */ + usi_01_cmgp: usi@15C22010 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x15C22010 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_01_CMGP_I2C */ + usi_01_cmgp_i2c: usi@15C22014 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x15C22014 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_02_CMGP */ + usi_02_cmgp: usi@15C22020 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x15C22020 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_02_CMGP_I2C */ + usi_02_cmgp_i2c: usi@15C22024 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x15C22024 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_03_CMGP */ + usi_03_cmgp: usi@15C22030 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x15C22030 0x4>; + /* usi_mode_v2 = "i2c" or "spi" or "uart" */ + status = "disabled"; + }; + + /* USI_03_CMGP_I2C */ + usi_03_cmgp_i2c: usi@15C22034 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x15C22034 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_I2C_CAM0 */ + usi_i2c_cam_0: usi@10821008 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821008 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_I2C_CAM1 */ + usi_i2c_cam_1: usi@1082100C { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x1082100C 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_I2C_CAM2 */ + usi_i2c_cam_2: usi@10821010 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821010 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_I2C_CAM3 */ + usi_i2c_cam_3: usi@10821014 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821014 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_SPI_CAM0 */ + usi_spi_cam_0: usi@10821004 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821004 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_UART_DBG */ + usi_uart_dbg: usi@10421000 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10421000 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* USI_UART_BT */ + usi_uart_bt: usi@10821000 { + compatible = "samsung,exynos-usi-v2"; + reg = <0x0 0x10821000 0x4>; + /* usi_mode_v2 = "i2c" */ + status = "disabled"; + }; + + /* PERIC1 CAM0 */ + hsi2c_0: hsi2c@10860000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10860000 0x1000>; + interrupts = <0 INTREQ__I2C_CAM0 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c0_bus>; + clocks = <&clock DOUT_CLK_PERIC1_I2C_CAM0>, <&clock GATE_I2C_CAM0>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpc0 0 0x1>; + gpio_sda= <&gpc0 1 0x1>; + status = "disabled"; + }; + + /* PERI1 CAM1 */ + hsi2c_1: hsi2c@10870000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10870000 0x1000>; + interrupts = <0 INTREQ__I2C_CAM1 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c1_bus>; + clocks = <&clock DOUT_CLK_PERIC1_I2C_CAM1>, <&clock GATE_I2C_CAM1>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpc0 2 0x1>; + gpio_sda= <&gpc0 3 0x1>; + status = "disabled"; + }; + + /* PERI1 CAM2 */ + hsi2c_2: hsi2c@10880000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10880000 0x1000>; + interrupts = <0 INTREQ__I2C_CAM2 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c2_bus>; + clocks = <&clock DOUT_CLK_PERIC1_I2C_CAM2>, <&clock GATE_I2C_CAM2>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpc0 4 0x1>; + gpio_sda= <&gpc0 5 0x1>; + status = "disabled"; + }; + + /* PERI1 CAM3 */ + hsi2c_3: hsi2c@10890000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10890000 0x1000>; + interrupts = <0 INTREQ__I2C_CAM3 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c3_bus>; + clocks = <&clock DOUT_CLK_PERIC1_I2C_CAM3>, <&clock GATE_I2C_CAM3>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpc0 6 0x1>; + gpio_sda= <&gpc0 7 0x1>; + status = "disabled"; + }; + + /* USI00_USI */ + hsi2c_4: hsi2c@10450000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10450000 0x1000>; + interrupts = <0 INTREQ__USI00_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c4_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI00_USI>, <&clock GATE_USI00_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp0 0 0x1>; + gpio_sda= <&gpp0 1 0x1>; + status = "disabled"; + }; + + /* USI00_USI_I2C */ + hsi2c_5: hsi2c@10460000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10460000 0x1000>; + interrupts = <0 INTREQ__USI00_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c5_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI_I2C>, <&clock GATE_USI00_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp0 2 0x1>; + gpio_sda= <&gpp0 3 0x1>; + status = "disabled"; + }; + + /* USI01_USI */ + hsi2c_6: hsi2c@10470000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10470000 0x1000>; + interrupts = <0 INTREQ__USI01_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c6_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI01_USI>, <&clock GATE_USI01_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp0 4 0x1>; + gpio_sda= <&gpp0 5 0x1>; + status = "disabled"; + }; + + /* USI01_USI_I2C */ + hsi2c_7: hsi2c@10480000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10480000 0x1000>; + interrupts = <0 INTREQ__USI01_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c7_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI_I2C>, <&clock GATE_USI01_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp0 6 0x1>; + gpio_sda= <&gpp0 7 0x1>; + status = "disabled"; + }; + + /* USI02_USI */ + hsi2c_8: hsi2c@10490000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10490000 0x1000>; + interrupts = <0 INTREQ__USI02_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c8_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI02_USI>, <&clock GATE_USI02_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp1 0 0x1>; + gpio_sda= <&gpp1 1 0x1>; + status = "disabled"; + }; + + /* USI02_USI_I2C */ + hsi2c_9: hsi2c@104A0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x104A0000 0x1000>; + interrupts = <0 INTREQ__USI02_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c9_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI_I2C>, <&clock GATE_USI02_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp1 2 0x1>; + gpio_sda= <&gpp1 3 0x1>; + status = "disabled"; + }; + + /* USI03_USI */ + hsi2c_10: hsi2c@104B0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x104B0000 0x1000>; + interrupts = <0 INTREQ__USI03_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c10_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI03_USI>, <&clock GATE_USI03_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp1 4 0x1>; + gpio_sda= <&gpp1 5 0x1>; + status = "disabled"; + }; + + /* USI03_USI_I2C */ + hsi2c_11: hsi2c@104C0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x104C0000 0x1000>; + interrupts = <0 INTREQ__USI03_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c11_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI_I2C>, <&clock GATE_USI03_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp1 6 0x1>; + gpio_sda= <&gpp1 7 0x1>; + status = "disabled"; + }; + + /* USI04_USI */ + hsi2c_12: hsi2c@104D0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x104D0000 0x1000>; + interrupts = <0 INTREQ__USI04_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c12_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI04_USI>, <&clock GATE_USI04_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp2 0 0x1>; + gpio_sda= <&gpp2 1 0x1>; + status = "disabled"; + }; + + /* USI04_USI_I2C */ + hsi2c_13: hsi2c@104E0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x104E0000 0x1000>; + interrupts = <0 INTREQ__USI04_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c13_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI_I2C>, <&clock GATE_USI04_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp2 2 0x1>; + gpio_sda= <&gpp2 3 0x1>; + status = "disabled"; + }; + + /* USI05_USI */ + hsi2c_14: hsi2c@104F0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x104F0000 0x1000>; + interrupts = <0 INTREQ__USI05_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c14_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI05_USI>, <&clock GATE_USI05_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp2 4 0x1>; + gpio_sda= <&gpp2 5 0x1>; + status = "disabled"; + }; + + /* USI05_USI_I2C */ + hsi2c_15: hsi2c@10500000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10500000 0x1000>; + interrupts = <0 INTREQ__USI05_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c15_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI_I2C>, <&clock GATE_USI05_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp2 6 0x1>; + gpio_sda= <&gpp2 7 0x1>; + status = "disabled"; + }; + + /* USI06_USI */ + hsi2c_16: hsi2c@108A0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x108A0000 0x1000>; + interrupts = <0 INTREQ__USI06_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c16_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI06_USI>, <&clock GATE_USI06_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp4 0 0x1>; + gpio_sda= <&gpp4 1 0x1>; + status = "disabled"; + }; + + /* USI06_USI_I2C */ + hsi2c_17: hsi2c@108B0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x108B0000 0x1000>; + interrupts = <0 INTREQ__USI06_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c17_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI_I2C>, <&clock GATE_USI06_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp4 2 0x1>; + gpio_sda= <&gpp4 3 0x1>; + status = "disabled"; + }; + + /* USI07_USI */ + hsi2c_18: hsi2c@108C0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x108C0000 0x1000>; + interrupts = <0 INTREQ__USI07_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c18_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI07_USI>, <&clock GATE_USI07_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp4 4 0x1>; + gpio_sda= <&gpp4 5 0x1>; + status = "disabled"; + }; + + /* USI07_USI_I2C */ + hsi2c_19: hsi2c@108D0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x108D0000 0x1000>; + interrupts = <0 INTREQ__USI07_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c19_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI_I2C>, <&clock GATE_USI07_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp4 6 0x1>; + gpio_sda= <&gpp4 7 0x1>; + status = "disabled"; + }; + + /* USI08_USI */ + hsi2c_20: hsi2c@108E0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x108E0000 0x1000>; + interrupts = <0 INTREQ__USI08_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c20_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI08_USI>, <&clock GATE_USI08_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp5 0 0x1>; + gpio_sda= <&gpp5 1 0x1>; + status = "disabled"; + }; + + /* USI08_USI_I2C */ + hsi2c_21: hsi2c@108F0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x108F0000 0x1000>; + interrupts = <0 INTREQ__USI08_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c21_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI_I2C>, <&clock GATE_USI08_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp5 2 0x1>; + gpio_sda= <&gpp5 3 0x1>; + status = "disabled"; + }; + + /* USI09_USI */ + hsi2c_22: hsi2c@10900000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10900000 0x1000>; + interrupts = <0 INTREQ__USI09_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c22_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI09_USI>, <&clock GATE_USI09_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp5 4 0x1>; + gpio_sda= <&gpp5 5 0x1>; + status = "disabled"; + }; + + /* USI09_USI_I2C */ + hsi2c_23: hsi2c@10910000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10910000 0x1000>; + interrupts = <0 INTREQ__USI09_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c23_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI_I2C>, <&clock GATE_USI09_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp5 6 0x1>; + gpio_sda= <&gpp5 7 0x1>; + status = "disabled"; + }; + + /* USI10_USI */ + hsi2c_24: hsi2c@10920000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10920000 0x1000>; + interrupts = <0 INTREQ__USI10_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c24_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI10_USI>, <&clock GATE_USI10_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp6 0 0x1>; + gpio_sda= <&gpp6 1 0x1>; + status = "disabled"; + }; + + /* USI10_USI_I2C */ + hsi2c_25: hsi2c@10930000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10930000 0x1000>; + interrupts = <0 INTREQ__USI10_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c25_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI_I2C>, <&clock GATE_USI10_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpp6 2 0x1>; + gpio_sda= <&gpp6 3 0x1>; + status = "disabled"; + }; + + /* USI11_USI */ + hsi2c_26: hsi2c@10940000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10940000 0x1000>; + interrupts = <0 INTREQ__USI11_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c26_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI11_USI>, <&clock GATE_USI11_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpg3 3 0x1>; + gpio_sda= <&gpg3 4 0x1>; + status = "disabled"; + }; + + /* USI11_USI_I2C */ + hsi2c_27: hsi2c@10950000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10950000 0x1000>; + interrupts = <0 INTREQ__USI11_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c27_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI_I2C>, <&clock GATE_USI11_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpg3 5 0x1>; + gpio_sda= <&gpg3 6 0x1>; + status = "disabled"; + }; + + /* USI12_USI */ + hsi2c_28: hsi2c@10520000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10520000 0x1000>; + interrupts = <0 INTREQ__USI12_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c28_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI12_USI>, <&clock GATE_USI12_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpg0 4 0x1>; + gpio_sda= <&gpg0 5 0x1>; + status = "disabled"; + }; + + /* USI12_USI_I2C */ + hsi2c_29: hsi2c@10530000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10530000 0x1000>; + interrupts = <0 INTREQ__USI12_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c29_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI_I2C>, <&clock GATE_USI12_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpg0 6 0x1>; + gpio_sda= <&gpg0 7 0x1>; + status = "disabled"; + }; + + /* USI13_USI */ + hsi2c_30: hsi2c@10540000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10540000 0x1000>; + interrupts = <0 INTREQ__USI13_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c30_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI13_USI>, <&clock GATE_USI13_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpg1 0 0x1>; + gpio_sda= <&gpg1 1 0x1>; + status = "disabled"; + }; + + /* USI13_USI_I2C */ + hsi2c_31: hsi2c@10550000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10550000 0x1000>; + interrupts = <0 INTREQ__USI13_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c31_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI_I2C>, <&clock GATE_USI13_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpg1 2 0x1>; + gpio_sda= <&gpg1 3 0x1>; + status = "disabled"; + }; + + /* USI14_USI */ + hsi2c_32: hsi2c@10560000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10560000 0x1000>; + interrupts = <0 INTREQ__USI14_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c32_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI14_USI>, <&clock GATE_USI14_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpg1 4 0x1>; + gpio_sda= <&gpg1 5 0x1>; + status = "disabled"; + }; + + /* USI14_USI_I2C */ + hsi2c_33: hsi2c@10570000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10570000 0x1000>; + interrupts = <0 INTREQ__USI14_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c33_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI_I2C>, <&clock GATE_USI14_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpg1 6 0x1>; + gpio_sda= <&gpg1 7 0x1>; + status = "disabled"; + }; + + /* USI15_USI */ + hsi2c_34: hsi2c@10580000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10580000 0x1000>; + interrupts = <0 INTREQ__USI15_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c34_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI15_USI>, <&clock GATE_USI15_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpg2 0 0x1>; + gpio_sda= <&gpg2 1 0x1>; + status = "disabled"; + }; + + /* USI15_USI_I2C */ + hsi2c_35: hsi2c@10590000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10590000 0x1000>; + interrupts = <0 INTREQ__USI15_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c35_bus>; + clocks = <&clock DOUT_CLK_PERIC0_USI_I2C>, <&clock GATE_USI15_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpg2 2 0x1>; + gpio_sda= <&gpg2 3 0x1>; + status = "disabled"; + }; + + /* USI16_USI */ + hsi2c_36: hsi2c@10970000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10970000 0x1000>; + interrupts = <0 INTREQ__USI16_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c36_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI16_USI>, <&clock GATE_USI16_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gph0 0 0x1>; + gpio_sda= <&gph0 1 0x1>; + status = "disabled"; + }; + + /* USI17_USI */ + hsi2c_37: hsi2c@10990000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x10990000 0x1000>; + interrupts = <0 INTREQ__USI17_USI 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c37_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI17_USI>, <&clock GATE_USI17_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gph0 4 0x1>; + gpio_sda= <&gph0 5 0x1>; + status = "disabled"; + }; + + /* USI17_USI_I2C */ + hsi2c_38: hsi2c@109A0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x109A0000 0x1000>; + interrupts = <0 INTREQ__USI17_I2C 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c38_bus>; + clocks = <&clock DOUT_CLK_PERIC1_USI_I2C>, <&clock GATE_USI17_I2C>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gph0 6 0x1>; + gpio_sda= <&gph0 7 0x1>; + status = "disabled"; + }; + + /* USI_CMGP00 */ + hsi2c_39: hsi2c@15D00000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x15D00000 0x1000>; + interrupts = <0 INTREQ__USI_CMGP0 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c39_bus>; + clocks = <&clock DOUT_CLK_USI_CMGP0>, <&clock GATE_USI_CMGP0>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpm0 0 0x1>; + gpio_sda= <&gpm1 0 0x1>; + status = "disabled"; + }; + + /* USI_CMGP00_I2C */ + hsi2c_40: hsi2c@15D10000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x15D10000 0x1000>; + interrupts = <0 INTREQ__I2C_CMGP0 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c40_bus>; + clocks = <&clock DOUT_CLK_I2C_CMGP0>, <&clock GATE_I2C_CMGP0>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpm2 0 0x1>; + gpio_sda= <&gpm3 0 0x1>; + status = "disabled"; + }; + + /* USI_CMGP01 */ + hsi2c_41: hsi2c@15D20000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x15D20000 0x1000>; + interrupts = <0 INTREQ__USI_CMGP1 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c41_bus>; + clocks = <&clock DOUT_CLK_USI_CMGP1>, <&clock GATE_USI_CMGP1>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpm4 0 0x1>; + gpio_sda= <&gpm5 0 0x1>; + status = "disabled"; + }; + + /* USI_CMGP01_I2C */ + hsi2c_42: hsi2c@15D30000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x15D30000 0x1000>; + interrupts = <0 INTREQ__I2C_CMGP1 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c42_bus>; + clocks = <&clock DOUT_CLK_I2C_CMGP1>, <&clock GATE_I2C_CMGP1>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpm6 0 0x1>; + gpio_sda= <&gpm7 0 0x1>; + status = "disabled"; + }; + + /* USI_CMGP02 */ + hsi2c_43: hsi2c@15D40000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x15D40000 0x1000>; + interrupts = <0 INTREQ__USI_CMGP2 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c43_bus>; + clocks = <&clock DOUT_CLK_USI_CMGP2>, <&clock GATE_USI_CMGP2>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpm8 0 0x1>; + gpio_sda= <&gpm9 0 0x1>; + status = "disabled"; + }; + + /* USI_CMGP02_I2C */ + hsi2c_44: hsi2c@15D50000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x15D50000 0x1000>; + interrupts = <0 INTREQ__I2C_CMGP2 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c44_bus>; + clocks = <&clock DOUT_CLK_I2C_CMGP2>, <&clock GATE_I2C_CMGP2>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpm10 0 0x1>; + gpio_sda= <&gpm11 0 0x1>; + status = "disabled"; + }; + + /* USI_CMGP03 */ + hsi2c_45: hsi2c@15D60000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x15D60000 0x1000>; + interrupts = <0 INTREQ__USI_CMGP3 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c45_bus>; + clocks = <&clock DOUT_CLK_USI_CMGP3>, <&clock GATE_USI_CMGP3>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpm12 0 0x1>; + gpio_sda= <&gpm13 0 0x1>; + status = "disabled"; + }; + + /* USI_CMGP03_I2C */ + hsi2c_46: hsi2c@15D70000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + default-clk = <200000000>; + reg = <0x0 0x15D70000 0x1000>; + interrupts = <0 INTREQ__I2C_CMGP3 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c46_bus>; + clocks = <&clock DOUT_CLK_I2C_CMGP3>, <&clock GATE_I2C_CMGP3>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + gpio_scl= <&gpm14 0 0x1>; + gpio_sda= <&gpm15 0 0x1>; + status = "disabled"; + }; + + /* SPI USI_PERIC1_SPI_CAM0 */ + spi_0: spi@10850000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x10850000 0x100>; + samsung,spi-fifosize = <256>; + interrupts = <0 INTREQ__SPI_CAM0 0>; +/* + dma-mode; + dmas = <&pdma0 25 &pdma0 24>; +*/ + dma-names = "tx", "rx"; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_SPI_CAM0>, <&clock DOUT_CLK_PERIC1_SPI_CAM0>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC0_USI00_SPI */ + spi_1: spi@10450000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x10450000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI00_USI 0>; +/* + dma-mode; + dmas = <&pdma0 1 &pdma0 0>; +*/ + dma-names = "tx", "rx"; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI00_USI>, <&clock DOUT_CLK_PERIC0_USI00_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC0_USI01_SPI */ + spi_2: spi@10470000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x10470000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI01_USI 0>; +/* + dma-mode; + dmas = <&pdma0 3 &pdma0 2>; +*/ + dma-names = "tx", "rx"; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI01_USI>, <&clock DOUT_CLK_PERIC0_USI01_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC0_USI02_SPI */ + spi_3: spi@10490000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x10490000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI02_USI 0>; +/* + dma-mode; + dmas = <&pdma0 5 &pdma0 4>; +*/ + dma-names = "tx", "rx"; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI02_USI>, <&clock DOUT_CLK_PERIC0_USI02_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC0_USI03_SPI */ + spi_4: spi@104B0000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x104B0000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI03_USI 0>; +/* + dma-mode; + dmas = <&pdma0 7 &pdma0 6>; +*/ + dma-names = "tx", "rx"; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI03_USI>, <&clock DOUT_CLK_PERIC0_USI03_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC0_USI04_SPI */ + spi_5: spi@104D0000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x104D0000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI04_USI 0>; +/* + dma-mode; + dmas = <&pdma0 9 &pdma0 8>; +*/ + dma-names = "tx", "rx"; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI04_USI>, <&clock DOUT_CLK_PERIC0_USI04_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC0_USI05_SPI */ + spi_6: spi@104F0000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x104F0000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI05_USI 0>; +/* + dma-mode; + dmas = <&pdma0 11 &pdma0 10>; +*/ + dma-names = "tx", "rx"; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI05_USI>, <&clock DOUT_CLK_PERIC0_USI05_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi6_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC1_USI06_SPI */ + spi_7: spi@108A0000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x108A0000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI06_USI 0>; +/* + dma-mode; + dmas = <&pdma0 15 &pdma0 14>; +*/ + dma-names = "tx", "rx"; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI06_USI>, <&clock DOUT_CLK_PERIC1_USI06_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi7_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC1_USI07_SPI */ + spi_8: spi@108C0000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x108C0000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI07_USI 0>; +/* + dma-mode; + dmas = <&pdma0 17 &pdma0 16>; +*/ + dma-names = "tx", "rx"; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI07_USI>, <&clock DOUT_CLK_PERIC1_USI07_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi8_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC1_USI08_SPI */ + spi_9: spi@108E0000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x108E0000 0x100>; + samsung,spi-fifosize = <256>; + interrupts = <0 INTREQ__USI08_USI 0>; +/* + dma-mode; + dmas = <&pdma0 19 &pdma0 18>; +*/ + dma-names = "tx", "rx"; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI08_USI>, <&clock DOUT_CLK_PERIC1_USI08_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi9_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC1_USI09_SPI */ + spi_10: spi@10900000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x10900000 0x100>; + samsung,spi-fifosize = <256>; + interrupts = <0 INTREQ__USI09_USI 0>; +/* + dma-mode; + dmas = <&pdma0 21 &pdma0 20>; +*/ + dma-names = "tx", "rx"; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI09_USI>, <&clock DOUT_CLK_PERIC1_USI09_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi10_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC1_USI10_SPI */ + spi_11: spi@10920000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x10920000 0x100>; + samsung,spi-fifosize = <256>; + interrupts = <0 INTREQ__USI10_USI 0>; +/* + dma-mode; + dmas = <&pdma0 23 &pdma0 22>; +*/ + dma-names = "tx", "rx"; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI10_USI>, <&clock DOUT_CLK_PERIC1_USI10_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi11_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC1_USI11_SPI */ + spi_12: spi@10940000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x10940000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI11_USI 0>; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI11_USI>, <&clock DOUT_CLK_PERIC1_USI11_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi12_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC0_USI12_SPI */ + spi_13: spi@10520000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x10520000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI12_USI 0>; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI12_USI>, <&clock DOUT_CLK_PERIC0_USI12_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi13_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC0_USI13_SPI */ + spi_14: spi@10540000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x10540000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI13_USI 0>; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI13_USI>, <&clock DOUT_CLK_PERIC0_USI13_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi14_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC0_USI14_SPI */ + spi_15: spi@10560000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x10560000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI14_USI 0>; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI14_USI>, <&clock DOUT_CLK_PERIC0_USI14_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi15_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC0_USI15_SPI */ + spi_16: spi@10580000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x10580000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI15_USI 0>; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI15_USI>, <&clock DOUT_CLK_PERIC0_USI15_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi16_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC1_USI16_SPI */ + spi_17: spi@10970000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x10970000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI16_USI 0>; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI16_USI>, <&clock DOUT_CLK_PERIC1_USI16_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi17_bus>; + status = "disabled"; + }; + + /* SPI USI_PERIC1_USI17_SPI */ + spi_18: spi@10990000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x10990000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI17_USI 0>; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI17_USI>, <&clock DOUT_CLK_PERIC1_USI17_USI>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi18_bus>; + status = "disabled"; + }; + + /* SPI USI_CMGP00 */ + spi_19: spi@15D00000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x15D00000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI_CMGP0 0>; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI_CMGP0>, <&clock DOUT_CLK_USI_CMGP0>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi19_bus>; + status = "disabled"; + }; + + /* SPI USI_CMGP01 */ + spi_20: spi@15D20000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x15D2000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI_CMGP1 0>; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI_CMGP1>, <&clock DOUT_CLK_USI_CMGP1>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi20_bus>; + status = "disabled"; + }; + + /* SPI USI_CMGP02 */ + spi_21: spi@15D40000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x15D40000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI_CMGP2 0>; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI_CMGP2>, <&clock DOUT_CLK_USI_CMGP2>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi21_bus>; + status = "disabled"; + }; + + /* SPI USI_CMGP03 */ + spi_22: spi@15D60000 { + compatible = "samsung,exynos-spi"; + reg = <0x0 0x15D60000 0x100>; + samsung,spi-fifosize = <64>; + interrupts = <0 INTREQ__USI_CMGP3 0>; + swap-mode; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock GATE_USI_CMGP3>, <&clock DOUT_CLK_USI_CMGP3>; + clock-names = "gate_spi_clk", "ipclk_spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi22_bus>; + status = "disabled"; + }; + + /* USI_PERIC0_UART_DBG */ + serial_0: uart@10440000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10440000 0x100>; + samsung,fifo-size = <256>; + interrupts = <0 INTREQ__UART_DBG 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + samsung,usi-serial-v2; + clocks = <&clock GATE_UART_DBG>, <&clock UART_DBG>; + clock-names = "gate_uart_clk0", "ipclk_uart0"; + status = "disabled"; + }; + + reboot { + compatible = "exynos,reboot"; + pmu_base = <0x15860000>; + }; + + /* USI_PERIC1_UART_BT */ + serial_1: uart@10840000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10840000 0x100>; + samsung,fifo-size = <256>; + interrupts = <0 INTREQ__UART_BT 0>; + pinctrl-names = "default", "rts"; + pinctrl-0 = <&uart1_bus_single>; /* or _bus_dual */ + pinctrl-1 = <&uart1_bus_rts>; + samsung,usi-serial-v2; + clocks = <&clock GATE_UART_BT>, <&clock DOUT_CLK_PERIC1_UART_BT>; + clock-names = "gate_uart_clk1", "ipclk_uart1"; + status = "disabled"; + }; + + /* USI_PERIC0_USI00_UART */ + serial_2: uart@10450000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10450000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI00_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI00_USI>, <&clock DOUT_CLK_PERIC0_USI00_USI>; + clock-names = "gate_uart_clk2", "ipclk_uart2"; + status = "disabled"; + }; + + /* USI_PERIC0_USI01_UART */ + serial_3: uart@10470000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10470000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI01_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI01_USI>, <&clock DOUT_CLK_PERIC0_USI01_USI>; + clock-names = "gate_uart_clk3", "ipclk_uart3"; + status = "disabled"; + }; + + /* USI_PERIC0_USI02_UART */ + serial_4: uart@10490000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10490000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI02_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI02_USI>, <&clock DOUT_CLK_PERIC0_USI02_USI>; + clock-names = "gate_uart_clk4", "ipclk_uart4"; + status = "disabled"; + }; + + /* USI_PERIC0_USI03_UART */ + serial_5: uart@104B0000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x104B0000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI03_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI03_USI>, <&clock DOUT_CLK_PERIC0_USI03_USI>; + clock-names = "gate_uart_clk5", "ipclk_uart5"; + status = "disabled"; + }; + + /* USI_PERIC0_USI04_UART */ + serial_6: uart@104D0000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x104D0000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI04_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart6_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI04_USI>, <&clock DOUT_CLK_PERIC0_USI04_USI>; + clock-names = "gate_uart_clk6", "ipclk_uart6"; + status = "disabled"; + }; + + /* USI_PERIC0_USI05_UART */ + serial_7: uart@104F0000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x104F0000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI05_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI05_USI>, <&clock DOUT_CLK_PERIC0_USI05_USI>; + clock-names = "gate_uart_clk7", "ipclk_uart7"; + status = "disabled"; + }; + + /* USI_PERIC1_USI06_UART */ + serial_8: uart@108A0000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x108A0000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI06_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart8_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI06_USI>, <&clock DOUT_CLK_PERIC1_USI06_USI>; + clock-names = "gate_uart_clk8", "ipclk_uart8"; + status = "disabled"; + }; + + /* USI_PERIC1_USI07_UART */ + serial_9: uart@108C0000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x108C0000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI07_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart9_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI07_USI>, <&clock DOUT_CLK_PERIC1_USI07_USI>; + clock-names = "gate_uart_clk9", "ipclk_uart9"; + status = "disabled"; + }; + + /* USI_PERIC1_USI08_UART */ + serial_10: uart@108E0000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x108E0000 0x100>; + samsung,fifo-size = <256>; + interrupts = <0 INTREQ__USI08_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart10_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI08_USI>, <&clock DOUT_CLK_PERIC1_USI08_USI>; + clock-names = "gate_uart_clk10", "ipclk_uart10"; + status = "disabled"; + }; + + /* USI_PERIC1_USI09_UART */ + serial_11: uart@10900000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10900000 0x100>; + samsung,fifo-size = <256>; + interrupts = <0 INTREQ__USI09_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart11_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI09_USI>, <&clock DOUT_CLK_PERIC1_USI09_USI>; + clock-names = "gate_uart_clk11", "ipclk_uart11"; + status = "disabled"; + }; + + /* USI_PERIC1_USI10_UART */ + serial_12: uart@10920000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10920000 0x100>; + samsung,fifo-size = <256>; + interrupts = <0 INTREQ__USI10_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart12_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI10_USI>, <&clock DOUT_CLK_PERIC1_USI10_USI>; + clock-names = "gate_uart_clk12", "ipclk_uart12"; + status = "disabled"; + }; + + /* USI_PERIC1_USI11_UART */ + serial_13: uart@10940000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10940000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI11_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart13_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI11_USI>, <&clock DOUT_CLK_PERIC1_USI11_USI>; + clock-names = "gate_uart_clk13", "ipclk_uart13"; + status = "disabled"; + }; + + /* USI_PERIC0_USI12_UART */ + serial_14: uart@10520000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10520000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI12_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart14_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI12_USI>, <&clock DOUT_CLK_PERIC0_USI12_USI>; + clock-names = "gate_uart_clk14", "ipclk_uart14"; + status = "disabled"; + }; + + /* USI_PERIC0_USI13_UART */ + serial_15: uart@10540000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10540000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI13_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart15_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI13_USI>, <&clock DOUT_CLK_PERIC0_USI13_USI>; + clock-names = "gate_uart_clk15", "ipclk_uart15"; + status = "disabled"; + }; + + /* USI_PERIC0_USI14_UART */ + serial_16: uart@10560000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10560000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI14_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart16_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI14_USI>, <&clock DOUT_CLK_PERIC0_USI14_USI>; + clock-names = "gate_uart_clk16", "ipclk_uart16"; + status = "disabled"; + }; + + /* USI_PERIC0_USI15_UART */ + serial_17: uart@10580000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10580000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI15_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart17_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI15_USI>, <&clock DOUT_CLK_PERIC0_USI15_USI>; + clock-names = "gate_uart_clk17", "ipclk_uart17"; + status = "disabled"; + }; + + /* USI_PERIC0_USI16_UART */ + serial_18: uart@10970000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10970000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI16_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart18_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI16_USI>, <&clock DOUT_CLK_PERIC1_USI16_USI>; + clock-names = "gate_uart_clk18", "ipclk_uart18"; + status = "disabled"; + }; + + /* USI_PERIC0_USI17_UART */ + serial_19: uart@10990000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x10990000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI17_USI 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart19_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI17_USI>, <&clock DOUT_CLK_PERIC1_USI17_USI>; + clock-names = "gate_uart_clk19", "ipclk_uart19"; + status = "disabled"; + }; + + /* USI_CMGP00_UART */ + serial_20: uart@15D00000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x15D00000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI_CMGP0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart20_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI_CMGP0>, <&clock DOUT_CLK_USI_CMGP0>; + clock-names = "gate_uart_clk20", "ipclk_uart20"; + status = "disabled"; + }; + + /* USI_CMGP01_UART */ + serial_21: uart@15D20000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x15D20000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI_CMGP1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart21_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI_CMGP1>, <&clock DOUT_CLK_USI_CMGP1>; + clock-names = "gate_uart_clk21", "ipclk_uart21"; + status = "disabled"; + }; + + /* USI_CMGP02_UART */ + serial_22: uart@15D40000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x15D40000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI_CMGP2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart22_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI_CMGP2>, <&clock DOUT_CLK_USI_CMGP2>; + clock-names = "gate_uart_clk22", "ipclk_uart22"; + status = "disabled"; + }; + + /* USI_CMGP03_UART */ + serial_23: uart@15D60000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + reg = <0x0 0x15D60000 0x100>; + samsung,fifo-size = <64>; + interrupts = <0 INTREQ__USI_CMGP3 0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart23_bus_single>; /* or _bus_dual */ + samsung,usi-serial-v2; + clocks = <&clock GATE_USI_CMGP3>, <&clock DOUT_CLK_USI_CMGP3>; + clock-names = "gate_uart_clk23", "ipclk_uart23"; + status = "disabled"; + }; + + udc: usb@10C00000 { + compatible = "samsung,exynos-dwusb"; + clocks = <&clock GATE_USB31DRD_SLV_LINK>, <&clock USB31DRD>; + clock-names = "aclk", "sclk"; + reg = <0x0 0x10C00000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + samsung,power-domain = <&pd_fsys0a>; + status = "disabled"; + + usbdrd_dwc3: dwc3 { + compatible = "synopsys,dwc3"; + reg = <0x0 0x10C00000 0x10000>; + interrupts = <0 INTREQ__USB31DRD_GIC_0 0>; + tx-fifo-resize = <0>; + adj-sof-accuracy = <0>; + is_not_vbus_pad = <1>; + enable_sprs_transfer = <1>; + phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + /* check susphy support */ + xhci_l2_support = <1>; + /* support usb audio offloading: 1, if not: 0 */ + usb_audio_offloading = <1>; + abox = <&abox>; /* Temporary block */ + /* support USB L2 sleep */ + ldos = <3>; + ldo_number = <10 11 12>; + /* INT min lock support */ + usb-pm-qos-int = <400000>; + }; + }; + + usbdrd_phy0: phy@10B00000 { + compatible = "samsung,exynos-usbdrd-phy"; + reg = <0x0 0x10B00000 0x200>, + <0x0 0x10AE0000 0x2800>, + <0x0 0x10AF0000 0x800>; + interrupts = <0 INTREQ__USB2_REMOTE_WAKEUP_GIC 0>, + <0 INTREQ__USB2_REMOTE_CONNECT_GIC 0>; + clocks = <&clock OSCCLK>, <&clock GATE_USB31DRD_SLV_LINK>; + clock-names = "ext_xtal", "aclk"; + samsung,pmu-syscon = <&pmu_system_controller>; + pmu_mask = <0x0>; + pmu_offset = <0x72c>; + pmu_offset_dp = <0x704>; + + /* USBDP combo phy version - 0x200 */ + phy_version = <0x301>; + /* if it doesn't need phy user mux, */ + /* you should write "none" */ + /* but refclk shouldn't be omitted */ + phyclk_mux = "none"; + phy_refclk = "ext_xtal"; + + /* if Main phy has the other phy, it must be set to 1. jusf for usbphy_info */ + has_other_phy = <0>; + /* if combo phy is used, it must be set to 1. usbphy_sub_info is enabled */ + has_combo_phy = <1>; + sub_phy_version = <0x400>; + + /* ip type */ + /* USB3DRD = 0 */ + /* USB3HOST = 1 */ + /* USB2DRD = 2 */ + /* USB2HOST = 3 */ + ip_type = <0x0>; + + /* for PHY CAL */ + /* choice only one item */ + phy_refsel_clockcore = <1>; + phy_refsel_ext_osc = <0>; + phy_refsel_xtal = <0>; + phy_refsel_diff_pad = <0>; + phy_refsel_diff_internal = <0>; + phy_refsel_diff_single = <0>; + + /* true : 1 , false : 0 */ + use_io_for_ovc = <0>; + common_block_disable = <1>; + is_not_vbus_pad = <1>; + used_phy_port = <0>; + + status = "disabled"; + + #phy-cells = <1>; + ranges; + }; + + sysreg_fsys1_controller: sysreg-controller@13C10000 { + compatible = "samsung,exynos8895-sysreg", "syscon"; + reg = <0x0 0x13C10000 0x1200>; + }; + + sysreg_fsys0_controller: sysreg-controller@13020000 { + compatible = "samsung,exynos8895-sysreg", "syscon"; + reg = <0x0 0x13020000 0x1200>; + }; + + sysmmu_pcie: sysmmu@13C20000 { + compatible = "samsung,pcie-sysmmu"; + reg = <0x0 0x13C20000 0x9000>; + interrupts = <0 INTREQ__SYSMMU_FSYS1_NS 0>; + clock-names = "aclk"; + clocks = <&clock GATE_SYSMMU_FSYS1>; + port-name = "PCIe"; + #iommu-cells = <0>; + ch-num = <0>; + }; + + sysmmu@13070000 { + compatible = "samsung,pcie-sysmmu"; + reg = <0x0 0x13070000 0x9000>; + interrupts = <0 INTREQ__SYSMMU_PCIE_GEN3A_NS 0>; + clock-names = "aclk"; + clocks = <&clock GATE_SYSMMU_PCIE_GEN3A>; + port-name = "PCIe"; + #iommu-cells = <0>; + ch-num = <1>; + }; + + pcie_0: pcie0@13ED0000 { + compatible = "samsung,exynos-pcie"; + gpios = <&gpf2 2 0x1 /* PERST */>; + reg = <0x0 0x13ED0000 0x1000 /* elbi base */ + 0x0 0x13EF0000 0x1000 /* phy base */ + 0x0 0x13C11044 0x10 /* sysreg base */ + 0x0 0x13F00000 0x1000 /* DBI base */ + 0x0 0x13EE0000 0x1FC /* phy pcs base */ + 0x0 0x14FFE000 0x2000 /* configuration space */ + 0x0 0x13EC0000 0x1000>; /* I/A space */ + reg-names = "elbi", "phy", "sysreg", "dbi", "pcs", "config", "ia"; + interrupts = <0 INTREQ__PCIE_WIFI0 0>; /* IRQ_PULSE */ + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,sysreg-phandle = <&sysreg_fsys1_controller>; + clocks = <&clock GATE_PCIE_GEN2_MSTR>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq &pcie0_perst>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + /* non-prefetchable memory */ + ranges = <0x82000000 0 0x14000000 0 0x14000000 0 0xFF0000>; + /* ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x20000000>; */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 INTREQ__PCIE_WIFI0 0x4>; + ip-ver = <0x982000>; + num-lanes = <1>; + ch-num = <0>; + pcie-clk-num = <0>; + phy-clk-num = <0>; + pcie-pm-qos-int = <0>; + use-cache-coherency = "false"; + use-msi = "false"; + use-sicd = "false"; + use-sysmmu = "false"; + use-ia = "true"; + max-link-speed = ; + status = "disabled"; + }; + + pcie_1: pcie1@13120000 { + compatible = "samsung,exynos-pcie-host-v1"; + gpios = <&gpf0 2 0x1 /* PERST */>; + reg = <0x0 0x13120000 0x1410 /* elbi base */ + 0x0 0x13150000 0x2000 /* phy base */ + 0x0 0x13020708 0x140 /* sysreg base */ + 0x0 0x13400000 0x300920 /* DBI base */ + 0x0 0x13140000 0x1FC /* phy pcs base */ + 0x0 0x11FFE000 0x2000 /* configuration space */ + 0x0 0x13100000 0x1000>; /* I/A space */ + reg-names = "elbi", "phy", "sysreg", "dbi", "pcs", "config", "ia"; + interrupts = <0 INTREQ__PCIE_GEN3A 0>; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,sysreg-phandle = <&sysreg_fsys0_controller>; + clocks = <&clock GATE_PCIE_GEN3_MSTR_SLV_A>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq &pcie1_perst>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + /* non-prefetchable memory */ + ranges = <0x82000000 0 0x11000000 0 0x11000000 0 0xFF0000>; + /* ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x20000000>; */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 INTREQ__PCIE_GEN3A 0x4>; + ip-ver = <0x982000>; + num-lanes = <2>; + ch-num = <1>; + pcie-clk-num = <0>; + phy-clk-num = <0>; + pcie-pm-qos-int = <0>; + use-cache-coherency = "false"; + use-msi = "false"; + use-sicd = "false"; + use-sysmmu = "false"; + use-ia = "false"; + max-link-speed = ; + status = "disabled"; + }; + + speedy: speedy@15970000 { + compatible = "samsung,exynos-speedy"; + reg = <0x0 0x15970000 0x2000>; + interrupts = <0 INTREQ__SPEEDY_APM 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&speedy_bus>; + status = "disabled"; + }; + + speedy1: speedy1@15980000 { + compatible = "samsung,exynos-speedy"; + reg = <0x0 0x15980000 0x2000>; + interrupts = <0 INTREQ__SPEEDY_SUB_APM 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&speedy1_bus>; + status = "disabled"; + }; + + watchdog_cl0@10050000 { + compatible = "samsung,exynos9-v1-wdt"; + reg = <0x0 0x10050000 0x100>; + interrupts = <0 INTREQ__WDT_CLUSTER0 0>; + clocks = <&clock OSCCLK>, <&clock GATE_WDT_CLUSTER0>; + clock-names = "rate_watchdog", "gate_watchdog"; + timeout-sec = <30>; + samsung,syscon-phandle = <&pmu_system_controller>; + index = <0>; /* if little cluster then index is 0*/ + }; + + watchdog_cl2@10060000 { + compatible = "samsung,exynos9-v2-wdt"; + reg = <0x0 0x10060000 0x100>; + interrupts = <0 INTREQ__WDT_CLUSTER2 0>; + clocks = <&clock OSCCLK>, <&clock GATE_WDT_CLUSTER2>; + clock-names = "rate_watchdog", "gate_watchdog"; + timeout-sec = <30>; + samsung,syscon-phandle = <&pmu_system_controller>; + index = <1>; /* if little cluster then index is 0*/ + use_multistage_wdt; /* Use FIQ debug watchdog */ + }; + + exynos_adc: adc@15C40000 { + compatible = "samsung,exynos-adc-v3"; + reg = <0x0 0x15C40000 0x100>; + interrupts = <0 INTREQ__ADC_CMGP2AP 0>; + #io-channel-cells = <1>; + io-channel-ranges; + clocks = <&clock GATE_ADC_CMGP_S0>; + clock-names = "gate_adcif"; + }; + + sec_pwm: pwm@10510000 { + compatible = "samsung,s3c6400-pwm"; + reg = <0x0 0x10510000 0x1000>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>, <4>; + #pwm-cells = <3>; + clocks = <&clock GATE_PWM>, <&clock OSCCLK>; + clock-names = "pwm_pclk", "pwm_sclk"; + status = "ok"; + }; + + dwmmc_2: dwmmc2@13D00000 { + compatible = "samsung,exynos-dw-mshc"; + reg = <0x0 0x13D00000 0x2000>; + reg-names = "dw_mmc"; + interrupts = <0 INTREQ__MMC_CARD 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock DOUT_CLK_FSYS1_MMC_CARD>, <&clock GATE_MMC_CARD>; + clock-names = "ciu", "ciu_gate"; + status = "disabled"; + }; + + rtc@15950000 { + compatible = "samsung,exynos8-rtc"; + reg = <0x0 0x15950000 0x100>; + interrupts = <0 INTREQ__RTC_ALARM_INT 0>, <0 INTREQ__RTC_TIC_INT_0 0>; + }; + + iommu-domain_aud { + compatible = "samsung,exynos-iommu-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + domain-clients = <&abox>; + }; + + fimg2d: g2d@18A20000 { + compatible = "samsung,exynos9820-g2d"; + reg = <0x0 0x18A20000 0xA000>; + interrupts = <0 INTREQ__G2D 0>; + clock-names = "gate"; + clocks = <&clock GATE_G2D>; + iommus = <&sysmmu_g2d0>, <&sysmmu_g2d1>; + hw_ppc = + /* sc_up none x1 x1/4 x1/9 x1/16 */ + <3400 3100 2200 3600 5100 7000 /* rgb32 non-rotated */ + 3300 2700 2000 3000 5200 6500 /* rgb32 rotated */ + 3000 2900 2600 3400 5100 11900 /* yuv2p non-rotated */ + 3200 2000 1900 3300 5200 7000 /* yuv2p rotated */ + 2400 1900 1900 2700 3100 4100 /* 8+2 non-rotated */ + 2500 900 900 2200 2900 3700 /* 8+2 rotated */ + 3800>; /* colorfill */ + + g2d_dvfs_table = <534000 711000 + 400000 534000 + 336000 400000 + 267000 356000 + 178000 200000 + 107000 134000 + >; + dma-coherent; + }; + + iommu-domain_g2d { + compatible = "samsung,exynos-iommu-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + domain-clients = <&fimg2d>; + }; + + iommu-domain_isp { + compatible = "samsung,exynos-iommu-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + domain-clients = <&fimc_is>, + <&fimc_is_sensor0>, + <&fimc_is_sensor1>, + <&fimc_is_sensor2>, + <&fimc_is_sensor3>, + <&fimc_is_sensor4>, + <&camerapp_gdc>; + }; + + iommu-domain_iva { + compatible = "samsung,exynos-iommu-bus"; + + /* #address-cells = <2>; */ + /* #size-cells = <1>; */ + /* ranges; */ + + #dma-address-cells = <1>; + #dma-size-cells = <1>; + /* start address, size */ + dma-window = <0x60000000 0x70000000>; + + domain-clients = <&iva>; + }; + + iva: iva@0x18200000 { + compatible = "samsung,iva"; + reg = <0x0 0x18200000 0x200000>; + + iommus = <&sysmmu_iva>; + + interrupt-names = "iva_mbox_irq"; + interrupts = <0 INTREQ__BLK_IVA_IVA_iva_ap_irq_aq_0 0>; + + clocks = <&clock GATE_IVA_IVA>; + clock-names = "clk_iva"; + + dvfs-dev = <&devfreq_6>; + qos_rate = <534000>; + + mcu-info { + mem_size = <0x20000>; + shmem_size = <0x1000>; + print_delay = <50>; /* us */ + }; + }; + + iommu-domain_mfc { + compatible = "samsung,exynos-iommu-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + domain-clients = <&mfc_0>, <&tsmux>; + }; + + tsmux: tsmux@188E0000 { + compatible = "samsung,exynos-tsmux"; + reg = <0x0 0x188E0000 0x1000>; + interrupts = <0 INTREQ__WFD 0>; + iommus = <&sysmmu_mfc1>; + }; + + repeater: repeater@0 { + compatible = "samsung,exynos-repeater"; + /* power domain */ + samsung,power-domain = <&pd_g2d>; + }; + + iommu-domain_mscl_smfc { + compatible = "samsung,exynos-iommu-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + domain-clients = <&scaler_0>, <&smfc>; + }; + + scaler_0: scaler@18B10000 { + compatible = "samsung,exynos5-scaler"; + reg = <0x0 0x18B10000 0x3000>; + interrupts = <0 INTREQ__MSCL 0>; + clocks = <&clock GATE_MSCL>; + clock-names = "gate"; + iommus = <&sysmmu_g2d2>; + }; + + smfc: smfc@18B00000 { + compatible = "samsung,exynos8890-jpeg"; + //dma-coherent; + reg = <0x0 0x18B00000 0x1000>; + interrupts = <0 INTREQ__JPEG 0>; + clocks = <&clock GATE_JPEG>; + clock-names = "gate"; + iommus = <&sysmmu_g2d2>; + smfc,int_qos_minlock = <534000>; + }; + + score: score@17D00000 { + compatible = "samsung,score"; + dma-coherent; + reg = <0x0 0x17D00000 0x80000>; + interrupts = <0 INTREQ__BLK_DSPM_SCORE_TS_II_o_INTERRUPT_TO_CPU 0>; + + clocks = <&clock GATE_SCORE_TS_II>, <&clock GATE_SCORE_BARON>; + clock-names = "dspm", "dsps"; + + iommus = <&sysmmu_score0>, <&sysmmu_score1>; + }; + + iommu-domain_score { + compatible = "samsung,exynos-iommu-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + domain-clients = <&score>; + }; + + npu: npu@17800000 { + compatible = "samsung,exynos-npu"; + iommus = <&sysmmu_npu>; + interrupts = <0 432 0>, <0 433 0>; + }; + + iommu-domain_npu { + compatible = "samsung,exynos-iommu-bus"; + #dma-address-cells = <1>; + #dma-size-cells = <1>; + /* start address, size */ + + /* DRAM mapping */ + dma-window = <0x80000000 0x40000000>; + domain-clients = <&npu>; + }; + + exynos_dm: exynos-dm@17000000 { + compatible = "samsung,exynos-dvfs-manager"; + reg = <0x0 0x17000000 0x0>; + acpm-ipc-channel = <1>; + dm_domains { + cpufreq_cl0 { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_cpu_cl0"; + }; + cpufreq_cl1 { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_cpu_cl1"; + }; + cpufreq_cl2 { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_cpu_cl2"; + }; + devfreq_mif { + dm-index = ; + available = "true"; + policy_use = "true"; + cal_id = ; + dm_type_name = "dm_mif"; + }; + devfreq_int { + dm-index = ; + available = "true"; + policy_use = "true"; + cal_id = ; + dm_type_name = "dm_int"; + }; + devfreq_intcam { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_intcam"; + }; + devfreq_cam { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_cam"; + }; + devfreq_iva { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_iva"; + }; + devfreq_score { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_score"; + }; + devfreq_disp { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_disp"; + }; + devfreq_aud { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_aud"; + }; + devfreq_mfc { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_mfc"; + }; + devfreq_NPU { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_npu"; + }; + dvfs_gpu { + dm-index = ; + available = "false"; + cal_id = ; + dm_type_name = "dm_gpu"; + }; + }; + }; + + cpuhp { + compatible = "exynos, cpuhp"; + fast_hp_cpus = "4-7"; + }; + + exynos_mode_changer { + enabled = <1>; + ctrl_type = <0>; /* 1 is FATS HP, 0 is legacy HP */ + + emc_modes { + emc_mode_0 { + mode_name = "QUAD"; + cpus = "0-7"; + max_freq = <1456000>; + boost_cpus = "6-7"; + change_latency = <15>; + enabled = <1>; + }; + emc_mode_1 { + mode_name = "DUAL"; + cpus = "0-3,6-7"; + boost_cpus = "6-7"; + max_freq = <1820000>; + change_latency = <30>; + ldsum_thr = <1200>; + enabled = <1>; + }; + emc_mode_2 { + mode_name = "SINGLE"; + cpus = "0-3,6"; + boost_cpus = "6"; + cal-id = ; + max_freq = <2080000>; + change_latency = <30>; + enabled = <1>; + }; + }; + + emc_domains { + emc_domain_0 { + domain_name = "LIT"; + cpus = "0-3"; + role = ; + cpu_heavy_thr = <255>; + cpu_idle_thr = <255>; + busy_ratio = <65>; + }; + emc_domain_1 { + domain_name = "MID"; + cpus = "4-5"; + role = ; + cpu_heavy_thr = <500>; + cpu_idle_thr = <200>; + busy_ratio = <0>; + }; + + emc_domain_2 { + domain_name = "BIG"; + cpus = "6-7"; + role = ; + cpu_heavy_thr = <650>; + cpu_idle_thr = <250>; + busy_ratio = <0>; + }; + }; + }; + + schedutil_gov { + schedutil_domain0: domain@0 { + device_type = "schedutil-domain"; + shared-cpus = "0-3"; + + enabled = <0>; /* Disabled */ + qos_min_class = <3>; + }; + + schedutil_domain1: domain@1 { + device_type = "schedutil-domain"; + shared-cpus = "4-5"; + + enabled = <1>; /* Enabled */ + expired_time = <80>; /* 80ms */ + qos_min_class = <5>; + }; + + schedutil_domain2: domain@2 { + device_type = "schedutil-domain"; + shared-cpus = "6-7"; + + enabled = <1>; /* Enabled */ + expired_time = <80>; /* 80ms */ + qos_min_class = <7>; + }; + }; + + schedutil { + domain@0 { + device_type = "freqvar-tune"; + shared-cpus = "0-3"; + + boost_table = < 0 >; + up_rate_limit_table = < 5 >; + down_rate_limit_table = < 5 >; + upscale_ratio_table = < 50 949000 65 1300000 80 >; + }; + domain@1 { + device_type = "freqvar-tune"; + shared-cpus = "4-5"; + + boost_table = < 0 >; + up_rate_limit_table = < 5 >; + down_rate_limit_table = < 5 >; + upscale_ratio_table = < 50 962000 65 1222000 80 >; + }; + domain@2 { + device_type = "freqvar-tune"; + shared-cpus = "6-7"; + + boost_table = < 0 >; + up_rate_limit_table = < 5 >; + down_rate_limit_table = < 5 >; + upscale_ratio_table = < 50 936000 65 1378000 80 >; + }; + }; + + cpufreq { + cpufreq_domain0: domain@0 { + device_type = "cpufreq-domain"; + sibling-cpus = "0-3"; + cal-id = ; + dm-type = ; + + max-freq = <1742000>; + min-freq = <442000>; + + /* PM QoS Class ID*/ + pm_qos-min-class = <3>; + pm_qos-max-class = <4>; + + user-default-qos = <806000>; + + #cooling-cells = <2>; /* min followed by max */ + + dm-constraints { + mif-perf { + const-type = ; + dm-type = ; + /* cpu mif */ + table = < 1950000 1794000 + 1846000 1794000 + 1742000 1794000 + 1586000 845000 + 1456000 845000 + 1300000 676000 + 1157000 676000 + 1053000 676000 + 949000 676000 + 806000 546000 + 650000 421000 + 546000 421000 + 442000 0 + >; + }; + }; + }; + + cpufreq_domain1: domain@1 { + device_type = "cpufreq-domain"; + sibling-cpus = "4-5"; + cal-id = ; + dm-type = ; + + max-freq = <1898000>; + min-freq = <507000>; + + /* PM QoS Class ID*/ + pm_qos-min-class = <5>; + pm_qos-max-class = <6>; + + user-default-qos = <845000>; + + #cooling-cells = <2>; /* min followed by max */ + + dm-constraints { + mif-perf { + const-type = ; + dm-type = ; + /* cpu mif */ + table = < 2002000 1794000 + 1898000 1794000 + 1794000 1794000 + 1690000 1794000 + 1586000 1794000 + 1508000 676000 + 1404000 676000 + 1222000 676000 + 1066000 676000 + 962000 546000 + 845000 546000 + 754000 421000 + 650000 0 + >; + }; + ank-perf { + const-type = ; + dm-type = ; + /* pmt ank */ + table = < 2002000 1053000 + 1898000 1053000 + 1794000 949000 + 1690000 949000 + 1586000 806000 + 1508000 806000 + 1404000 806000 + 1222000 650000 + 1066000 650000 + 962000 0 + 845000 0 + 754000 0 + 650000 0 + >; + }; + }; + }; + + cpufreq_domain2: domain@2 { + device_type = "cpufreq-domain"; + sibling-cpus = "6-7"; + cal-id = ; + dm-type = ; + need-awake; + + max-freq = <1456000>; + min-freq = <520000>; + + /* PM QoS Class ID*/ + pm_qos-min-class = <7>; + pm_qos-max-class = <8>; + + user-default-qos = <936000>; + + #cooling-cells = <2>; /* min followed by max */ + + dm-constraints { + mif-perf { + const-type = ; + dm-type = ; + /* cpu mif */ + table = < 2600000 1794000 + 2470000 1794000 + 2340000 1794000 + 2236000 1794000 + 2080000 1794000 + 1976000 1794000 + 1820000 1794000 + 1664000 1794000 + 1560000 1794000 + 1456000 1539000 + 1378000 1539000 + 1248000 1539000 + 1144000 1014000 + 1040000 1014000 + 936000 845000 + 819000 845000 + 728000 0 + 624000 0 + 520000 0 + >; + }; + }; + }; + + }; + + exynos_devfreq { + compatible = "samsung,exynos-devfreq-root"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + devfreq_0: devfreq_mif@17000010 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000010 0x0>; + devfreq_type = ; + devfreq_domain_name = "dvfs_mif"; + pm_qos_class = <15>; /* PM_QOS_BUS_THROUGHPUT */ + pm_qos_class_max = <16>; /* PM_QOS_BUS_THROUGHPUT_MAX */ + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "true"; + delay_time_list = "20"; + + freq_info = <2094000 421000 421000 421000 2094000 421000>; + /* initial_freq, default_qos, suspend_freq, min_freq, max_freq reboot_freq */ + + /* Booting value */ + boot_info = <40 2093000>; + /* boot_qos_timeout, boot_freq */ + + /* governor data */ + governor = ; + + bts_update = "true"; + dfs_id = ; + acpm-ipc-channel = <1>; + use_acpm = "true"; + update_fvp = "true"; + }; + + devfreq_1: devfreq_int@17000020 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000020 0x0>; + devfreq_type = ; + devfreq_domain_name = "dvfs_int"; + pm_qos_class = <11>; /* PM_QOS_DEVICE_THROUGHPUT */ + pm_qos_class_max = <13>; /* PM_QOS_DEVICE_THROUGHPUT_MAX */ + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <534000 200000 100000 100000 534000 534000>; + /* */ + + /* Booting value */ + boot_info = <40 534000>; + /* boot_qos_timeout, boot_freq */ + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + acpm-ipc-channel = <1>; + use_acpm = "true"; + }; + + devfreq_2: devfreq_intcam@17000030 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000030 0x0>; + devfreq_type = ; + devfreq_domain_name = "dvfs_intcam"; + pm_qos_class = <12>; /* PM_QOS_INTCAM_THROUGHPUT */ + pm_qos_class_max = <14>; /* PM_QOS_INTCAM_THROUGHPUT_MAX */ + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <690000 650000 650000 650000 690000 690000>; + /* */ + + /* Booting value */ + boot_info = <40 650000>; + /* boot_qos_timeout, boot_freq */ + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + }; + + devfreq_3: devfreq_disp@17000040 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000040 0x0>; + devfreq_type = ; + devfreq_domain_name = "dvfs_disp"; + pm_qos_class = <19>; /* PM_QOS_DISPLAY_THROUGHPUT */ + pm_qos_class_max = <20>; /* PM_QOS_DISPLAY_THROUGHPUT_MAX */ + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <640000 134000 134000 134000 640000 640000>; + /* */ + + /* Booting value */ + boot_info = <40 640000>; + /* boot_qos_timeout, boot_freq */ + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + }; + + devfreq_4: devfreq_cam@17000050 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000050 0x0>; + devfreq_type = ; + devfreq_domain_name = "dvfs_cam"; + pm_qos_class = <21>; /* PM_QOS_CAM_THROUGHPUT */ + pm_qos_class_max = <26>; /* PM_QOS_CAM_THROUGHPUT_MAX */ + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <690000 650000 650000 650000 690000 690000>; + /* */ + + /* Booting value */ + boot_info = <40 650000>; + /* boot_qos_timeout, boot_freq */ + + /* governor data */ + governor = ; + + bts_update = "false"; + + dfs_id = ; + }; + + devfreq_5: devfreq_aud@17000060 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000060 0x0>; + devfreq_type = ; + devfreq_domain_name = "dvfs_aud"; + pm_qos_class = <22>; /* PM_QOS_AUD_THROUGHPUT */ + pm_qos_class_max = <27>; /* PM_QOS_AUD_THROUGHPUT_MAX */ + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <1180000 295000 295000 295000 1180000 295000>; + /* */ + + /* Booting value */ + boot_info = <0 295000>; + /* boot_qos_timeout, boot_freq */ + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + + samsung,power-domain = <&pd_aud>; + pd_name = "pd-aud"; + }; + + devfreq_6: devfreq_iva@17000070 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000070 0x0>; + devfreq_type = ; + devfreq_domain_name = "dvfs_iva"; + pm_qos_class = <23>; /* PM_QOS_IVA_THROUGHPUT */ + pm_qos_class_max = <28>; /* PM_QOS_IVA_THROUGHPUT_MAX */ + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <56000 56000 56000 56000 534000 56000>; + /* */ + + /* Booting value */ + boot_info = <40 56000>; + /* boot_qos_timeout, boot_freq */ + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + }; + + devfreq_7: devfreq_score@17000080 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000080 0x0>; + devfreq_type = ; + devfreq_domain_name = "dvfs_score"; + pm_qos_class = <24>; /* PM_QOS_SCORE_THROUGHPUT */ + pm_qos_class_max = <29>; /* PM_QOS_SOCRE_THROUGHPUT_MAX */ + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <25000 25000 25000 25000 666000 25000>; + /* */ + + /* Booting value */ + boot_info = <40 25000>; + /* boot_qos_timeout, boot_freq */ + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + }; + + devfreq_8: devfreq_mfc@17000090 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000090 0x0>; + devfreq_type = ; + devfreq_domain_name = "dvfs_mfc"; + pm_qos_class = <31>; /* PM_QOS_MFC_THROUGHPUT */ + pm_qos_class_max = <33>; /* PM_QOS_MFC_THROUGHPUT_MAX */ + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <134000 134000 134000 134000 666000 134000>; + /* */ + + /* Booting value */ + boot_info = <40 134000>; + /* boot_qos_timeout, boot_freq */ + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + }; + devfreq_9: devfreq_npu@170000A0 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x170000A0 0x0>; + devfreq_type = ; + devfreq_domain_name = "dvfs_npu"; + pm_qos_class = <32>; /* PM_QOS_NPU_THROUGHPUT */ + pm_qos_class_max = <34>; /* PM_QOS_NPU_THROUGHPUT_MAX */ + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <167000 167000 167000 167000 800000 167000>; + /* */ + + /* Booting value */ + boot_info = <0 167000>; + /* boot_qos_timeout, boot_freq */ + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + + samsung,power-domain = <&pd_npu1>; + pd_name = "pd-npu1"; + }; + }; + + tmuctrl_0: BIG@10090000 { + compatible = "samsung,exynos9820-tmu"; + reg = <0x0 0x10090000 0x800>; + interrupts = <0 INTREQ__TMU_TMU_TOP 0>; + tmu_name = "BIG"; + id = <0>; + sensors = <1984>; /* 0x7C0 */ + sensing_mode = "balance"; + hotplug_enable = <1>; + hotplug_in_threshold = <91>; + hotplug_out_threshold = <96>; + #include "exynos9810-tmu-sensor-conf.dtsi" + }; + + tmuctrl_1: MID@10090000 { + compatible = "samsung,exynos9820-tmu"; + reg = <0x0 0x10090000 0x800>; + interrupts = <0 INTREQ__TMU_TMU_TOP 0>; + tmu_name = "MID"; + id = <1>; + sensors = <32>; /* 0x20 */ + sensing_mode = "max"; + #include "exynos9810-tmu-sensor-conf.dtsi" + }; + + tmuctrl_2: LITTLE@10090000 { + compatible = "samsung,exynos9820-tmu"; + reg = <0x0 0x10090000 0x800>; + interrupts = <0 INTREQ__TMU_TMU_TOP 0>; + tmu_name = "LITTLE"; + id = <2>; + sensors = <16>; /* 0x10 */ + sensing_mode = "max"; + #include "exynos9810-tmu-sensor-conf.dtsi" + }; + + tmuctrl_3: G3D@100A0000 { + compatible = "samsung,exynos9810-tmu"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <0 INTREQ__TMU_TMU_SUB 0>; + tmu_name = "G3D"; + id = <3>; + sensors = <62>; /* 0x3E */ + sensing_mode = "balance"; + #include "exynos9810-tmu-sensor-conf.dtsi" + }; + + tmuctrl_4: ISP@100A0000 { + compatible = "samsung,exynos9810-tmu"; + reg = <0x0 0x100A0000 0x800>; + interrupts = <0 INTREQ__TMU_TMU_SUB 0>; + tmu_name = "ISP"; + id = <4>; + sensors = <256>; /* 0x100 */ + sensing_mode = "max"; + #include "exynos9810-tmu-sensor-conf.dtsi" + }; + + acpm_tmu { + acpm-ipc-channel = <9>; + }; + + thermal-zones { + big_thermal: BIG { + zone_name = "BIG_THERMAL"; + polling-delay-passive = <50>; + polling-delay = <1000>; + thermal-sensors = <&tmuctrl_0>; + governor = "power_allocator"; + sustainable-power = <0>; + k_po = <0>; + k_pu = <0>; + k_i = <0>; + i_max = <0>; + integral_cutoff = <0>; + + trips { + big_cold: big-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_switch_on: big-switch-on { + temperature = <55000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_control_temp: big-control-temp { + temperature = <83000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + big_alert0: big-alert0 { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_alert1: big-alert1 { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_alert2: big-alert2 { + temperature = <105000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_alert3: big-alert3 { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_hot: big-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&big_control_temp>; + cooling-device = <&cpufreq_domain2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + }; + + mid_thermal: MID { + zone_name = "MID_THERMAL"; + polling-delay-passive = <50>; + polling-delay = <1000>; + thermal-sensors = <&tmuctrl_1>; + governor = "power_allocator"; + sustainable-power = <0>; + k_po = <0>; + k_pu = <0>; + k_i = <0>; + i_max = <0>; + integral_cutoff = <0>; + + trips { + mid_cold: mid-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_switch_on: mid-switch-on { + temperature = <55000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_control_temp: mid-control-temp { + temperature = <83000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + mid_alert0: mid-alert0 { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_alert1: mid-alert1 { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_alert2: mid-alert2 { + temperature = <105000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_alert3: mid-alert3 { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_hot: mid-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&mid_control_temp>; + cooling-device = <&cpufreq_domain1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + little_thermal: LITTLE { + zone_name = "LITTLE_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_2>; + + trips { + little_alert0: little-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_alert1: little-alert1 { + temperature = <76000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_alert2: little-alert2 { + temperature = <81000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_alert3: little-alert3 { + temperature = <86000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_alert4: little-alert4 { + temperature = <91000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_alert5: little-alert5 { + temperature = <96000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_alert6: little-alert6 { + temperature = <101000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_hot: little-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&little_alert0>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + map1 { + trip = <&little_alert1>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + map2 { + trip = <&little_alert2>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + map3 { + trip = <&little_alert3>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + map4 { + trip = <&little_alert4>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + map5 { + trip = <&little_alert5>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + map6 { + trip = <&little_alert6>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + map7 { + trip = <&little_hot>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + }; + }; + + gpu_thermal: G3D { + zone_name = "G3D_THERMAL"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_3>; + governor = "power_allocator"; + sustainable-power = <0>; + k_po = <0>; + k_pu = <0>; + k_i = <0>; + i_max = <0>; + integral_cutoff = <0>; + + trips { + gpu_cold: gpu-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_switch_on: gpu-switch-on { + temperature = <78000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_control_temp: gpu-control-temp { + temperature = <88000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert0: gpu-alert0 { + temperature = <105000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_alert1: gpu-alert1 { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_alert2: gpu-alert2 { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_alert3: gpu-alert3 { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_hot: gpu-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&gpu_control_temp>; + cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + isp_thermal: ISP { + zone_name = "ISP_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_4>; + + trips { + isp_alert0: isp-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert1: isp-alert1 { + temperature = <91000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert2: isp-alert2 { + temperature = <96000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert3: isp-alert3 { + temperature = <101000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert4: isp-alert4 { + temperature = <101000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert5: isp-alert5 { + temperature = <101000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert6: isp-alert6 { + temperature = <101000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_hot: isp-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&isp_alert0>; + cooling-device = <&fimc_is 0 0>; + }; + map1 { + trip = <&isp_alert1>; + cooling-device = <&fimc_is 0 0>; + }; + map2 { + trip = <&isp_alert2>; + cooling-device = <&fimc_is 0 0>; + }; + map3 { + trip = <&isp_alert3>; + cooling-device = <&fimc_is 0 0>; + }; + map4 { + trip = <&isp_alert4>; + cooling-device = <&fimc_is 0 0>; + }; + map5 { + trip = <&isp_alert5>; + cooling-device = <&fimc_is 0 0>; + }; + map6 { + trip = <&isp_alert6>; + cooling-device = <&fimc_is 0 0>; + }; + map7 { + trip = <&isp_hot>; + cooling-device = <&fimc_is 0 0>; + }; + }; + }; + + }; + + seclog { + compatible = "samsung,exynos-seclog"; + interrupts = <0 224 0>; + }; + + /* tbase */ + tee { + compatible = "samsung,exynos-tee"; + interrupts = <0 223 0>; + }; + + /* Secure RPMB */ + ufs-srpmb { + compatible = "samsung,ufs-srpmb"; + interrupts = <0 460 0>; + }; + + smc_info: mcinfo@1BC300000 { + compatible = "samsung,exynos-mcinfo"; + reg = <0x0 0x1BC3004C 0x4>, + <0x0 0x1BD3004C 0x4>, + <0x0 0x1BE3004C 0x4>, + <0x0 0x1BF3004C 0x4>; + bit_field = <24 5>; + /* start bit, width */ + basecnt = <4>; + irqcnt = <4>; + + interrupts = <0 INTREQ__DMC_TEMPERR_MIF0 0>, + <0 INTREQ__DMC_TEMPERR_MIF1 0>, + <0 INTREQ__DMC_TEMPERR_MIF2 0>, + <0 INTREQ__DMC_TEMPERR_MIF3 0>; + }; + + exynos-bcmdbg { + compatible = "samsung,exynos-bcm_dbg"; + + pd-name = "pd-trex", "pd-aud", "pd-dpu", "pd-dspm", "pd-fsys0", + "pd-fsys1", "pd-g2d", "pd-embedded_g3d", "pd-isphq", "pd-isplp", + "pd-isppre", "pd-iva", "pd-mfc", "pd-npu0"; + + max_define_event = ; + /* define_event_index ev0 ev1 ev2 ev3 ev4 ev5 ev6 ev7 */ + define_events = , + , + , + , + , + , + ; + default_define_event = ; + + /* sm_id_mask sm_id_value */ + define_filter_id = , + , + , + , + , + , + ; + /* ev0 ev1 ev2 ev3 ev4 ev5 ev6 ev7 */ + define_filter_id_active = , + , + , + , + , + , + ; + /* sm_other_type0 sm_other_mask0 sm_other_value0 */ + define_filter_other_0 = , + , + , + , + , + , + ; + /* sm_other_type1 sm_other_mask1 sm_other_value1 */ + define_filter_other_1 = , + , + , + , + , + , + ; + /* ev0 ev1 ev2 ev3 ev4 ev5 ev6 ev7 */ + define_filter_other_active = , + , + , + , + , + , + ; + + /* peak_mask peak_id */ + define_sample_id = , + , + , + , + , + , + ; + /* ev0 ev1 ev2 ev3 ev4 ev5 ev6 ev7 */ + define_sample_id_enable = , + , + , + , + , + , + ; + + bcm_ip_nr = <46>; + initial_run_bcm_ip = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, + <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>, + <31>, <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>, <40>, + <41>, <42>, <43>, <44>, <45>; + initial_bcm_run = ; + /* msec (max 500msec) */ + initial_period = <1>; + initial_bcm_mode = ; + available_stop_owner = ; + buff_size = <0x100000>; + + ipc_bcm_event { + plugin-len = <5>; + plugin-name = "BCM"; + }; + }; + + mailbox_vts: mailbox@0x155a0000 { + compatible = "samsung,mailbox-asoc"; + reg = <0x0 0x155a0000 0x01000>; + reg-names = "sfr"; + interrupts = <0 430 0>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + vts: vts@0x15510000 { + compatible = "samsung,vts"; + reg = <0x0 0x15510000 0x1004>, <0x0 0x15420000 0x10010>, + <0x0 0x15570000 0x8>, <0x0 0x155d0000 0x8>, <0x0 0x15600000 0x101400>, + <0x0 0x155f0000 0x50>; + reg-names = "sfr", "baaw", "dmic", "dmic_3rd", "sram", "gpr"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + pinctrl-names = "dmic_default", "amic_default", "idle"; + pinctrl-0 = <&dmic_3rd_bus_clk &amic_pdm>; + pinctrl-1 = <&dmic_bus_clk &dmic_pdm>; + pinctrl-2 = <&dmic_3rd_bus_clk_idle &mic_bus_clk_idle &dmic_pdm_idle &amic_pdm_idle>; + samsung,power-domain = <&pd_vts>; + clocks = <&clock UMUX_CLKCMU_VTS_RCO>, <&clock DOUT_CLK_VTS_DMIC>, + <&clock DOUT_CLK_VTS_DMIC_IF>, <&clock DOUT_CLK_VTS_DMIC_DIV2>; + clock-names = "rco", "dmic", "dmic_if", "dmic_sync"; + mailbox = <&mailbox_vts>; + #sound-dai-cells = <1>; + interrupt-parent = <&mailbox_vts>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>; + interrupt-names = "error", "boot_completed", "ipc_received", "voice_triggered", + "trigger_period_elapsed", "record_period_elapsed", + "debuglog_bufzero", "debuglog_bufone", + "audio_dump", "log_dump"; + vts_dma0: vts_dma@0 { + compatible = "samsung,vts-dma"; + vts = <&vts>; + id = <0>; + type = "vts-trigger"; + }; + + vts_dma1: vts_dma@1 { + compatible = "samsung,vts-dma"; + vts = <&vts>; + id = <1>; + type = "vts-record"; + }; + }; + + displayport_adma: dp_dma { + compatible = "samsung,displayport-adma"; + + /* dma-mode; */ + dmas = <&pdma0 28>; + dma-names = "tx"; + }; +};