From: Jim Bride Date: Tue, 8 Aug 2017 21:51:34 +0000 (-0700) Subject: drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=912d64123d354dd2e4ced479e1d93e74ea4c99a8;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init Bit 29 of SRD_CTL needs to have its value preserved according to the B-Spec, so right before we write out the register we go ahead and read the register and preserve the value of that bit before we write out the configured register value. v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo) Cc: Rodrigo Vivi Cc: Chris Wilson Cc: Jani Nikula Signed-off-by: Jim Bride Reviewed-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/1502229094-13392-1-git-send-email-jim.bride@linux.intel.com --- diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b2546ade2c45..56df86ef5a4d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3872,6 +3872,7 @@ enum { #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0) #define EDP_PSR_ENABLE (1<<31) #define BDW_PSR_SINGLE_FRAME (1<<30) +#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */ #define EDP_PSR_LINK_STANDBY (1<<27) #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 559f1ab42bfc..1b31ab002dae 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp) else val |= EDP_PSR_TP1_TP2_SEL; + val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; I915_WRITE(EDP_PSR_CTL, val); }