From: Ralf Baechle Date: Thu, 20 Dec 2012 11:47:51 +0000 (+0100) Subject: Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores." X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=9120963578320532dfb3a9a7947e8d05b39900b5;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git Revert "MIPS: Optimise TLB handlers for MIPS32/64 R2 cores." This reverts commit ff401e52100dcdc85e572d1ad376d3307b3fe28e. This breaks on MIPS64 R2 cores such as Broadcom's. --- diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 05613355627b..1c8ac49ec72c 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -976,13 +976,6 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) #endif uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); - - if (cpu_has_mips_r2) { - uasm_i_ext(p, tmp, tmp, PGDIR_SHIFT, (32 - PGDIR_SHIFT)); - uasm_i_ins(p, ptr, tmp, PGD_T_LOG2, (32 - PGDIR_SHIFT)); - return; - } - uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ @@ -1018,15 +1011,6 @@ static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) { - if (cpu_has_mips_r2) { - /* PTE ptr offset is obtained from BadVAddr */ - UASM_i_MFC0(p, tmp, C0_BADVADDR); - UASM_i_LW(p, ptr, 0, ptr); - uasm_i_ext(p, tmp, tmp, PAGE_SHIFT+1, PGDIR_SHIFT-PAGE_SHIFT-1); - uasm_i_ins(p, ptr, tmp, PTE_T_LOG2+1, PGDIR_SHIFT-PAGE_SHIFT-1); - return; - } - /* * Bug workaround for the Nevada. It seems as if under certain * circumstances the move from cp0_context might produce a