From: Kirill A. Shutemov Date: Tue, 15 Sep 2009 09:23:53 +0000 (+0100) Subject: ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=910a17e57ab6cd22b300bde4ce5f633f175c7ccd;p=GitHub%2FLineageOS%2Fandroid_kernel_samsung_universal7580.git ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5. It's not true at least for CPUs based on Cortex-A8. List of CPUs with cache line size != 32 should be expanded later. Signed-off-by: Kirill A. Shutemov Signed-off-by: Russell King --- diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index feaa75f0013..66c160b8547 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -4,7 +4,7 @@ #ifndef __ASMARM_CACHE_H #define __ASMARM_CACHE_H -#define L1_CACHE_SHIFT 5 +#define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) /* diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 5fe595aeba6..8d43e58f924 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -771,3 +771,8 @@ config CACHE_XSC3L2 select OUTER_CACHE help This option enables the L2 cache on XScale3. + +config ARM_L1_CACHE_SHIFT + int + default 6 if ARCH_OMAP3 + default 5