From: Maciej W. Rozycki Date: Tue, 2 Jun 2015 16:50:59 +0000 (+0100) Subject: MIPS: Avoid an FPE exception in FCSR mask probing X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=90b712ddabb40c49ca4f68bab07e27aa34c8d2a3;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git MIPS: Avoid an FPE exception in FCSR mask probing Use the default FCSR value in mask probing, avoiding an FPE exception where reset has left any exception enable and their corresponding cause bits set and the register is then rewritten with these bits active. Signed-off-by: Maciej W. Rozycki Cc: Joshua Kinard Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index e36515dcd3b2..209e5b76c1bc 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -74,13 +74,12 @@ static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) { unsigned long sr, mask, fcsr, fcsr0, fcsr1; + fcsr = c->fpu_csr31; mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; sr = read_c0_status(); __enable_fpu(FPU_AS_IS); - fcsr = read_32bit_cp1_register(CP1_STATUS); - fcsr0 = fcsr & mask; write_32bit_cp1_register(CP1_STATUS, fcsr0); fcsr0 = read_32bit_cp1_register(CP1_STATUS);