From: Joe Perches Date: Wed, 25 Mar 2015 19:54:26 +0000 (-0700) Subject: staging: rts5208: Remove RTSX_READ_REG and RTSX_WRITE_REG macros X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=8ee775f92c8af2eb1626d39f06feac04fe0cb6e0;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git staging: rts5208: Remove RTSX_READ_REG and RTSX_WRITE_REG macros Macros with hidden flow control are bad form as the code path taken can be unexpected for the reader. Expand these in-place and remove the macros. Done with coccinelle script: @@ expression chip; expression arg1; expression arg2; expression arg3; @@ - RTSX_WRITE_REG(chip, arg1, arg2, arg3); + retval = rtsx_write_register(chip, arg1, arg2, arg3); + if (retval) { + rtsx_trace(chip); + return retval; + } @@ expression chip; expression arg1; expression arg2; @@ - RTSX_READ_REG(chip, arg1, arg2); + retval = rtsx_read_register(chip, arg1, arg2); + if (retval) { + rtsx_trace(chip); + return retval; + } Signed-off-by: Joe Perches Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/rts5208/ms.c b/drivers/staging/rts5208/ms.c index dcaec195cdcc..ee818b0dc401 100644 --- a/drivers/staging/rts5208/ms.c +++ b/drivers/staging/rts5208/ms.c @@ -169,7 +169,11 @@ static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode, return retval; } - RTSX_READ_REG(chip, MS_TRANS_CFG, &val); + retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) { rtsx_trace(chip); return STATUS_FAIL; @@ -424,25 +428,71 @@ static int ms_switch_clock(struct rtsx_chip *chip) static int ms_pull_ctl_disable(struct rtsx_chip *chip) { + int retval; + if (CHECK_PID(chip, 0x5208)) { - RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, - MS_D1_PD | MS_D2_PD | MS_CLK_PD | MS_D6_PD); - RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, - MS_D3_PD | MS_D0_PD | MS_BS_PD | XD_D4_PD); - RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, - MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); - RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, - XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); - RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, - MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); - RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, - MS_D5_PD | MS_D4_PD); + retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, + MS_D1_PD | MS_D2_PD | MS_CLK_PD | MS_D6_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, + MS_D3_PD | MS_D0_PD | MS_BS_PD | XD_D4_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, + MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, + XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, + MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, + MS_D5_PD | MS_D4_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } } else if (CHECK_PID(chip, 0x5288)) { if (CHECK_BARO_PKG(chip, QFN)) { - RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55); - RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55); - RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B); - RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69); + retval = rtsx_write_register(chip, CARD_PULL_CTL1, + 0xFF, 0x55); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL2, + 0xFF, 0x55); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL3, + 0xFF, 0x4B); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL4, + 0xFF, 0x69); + if (retval) { + rtsx_trace(chip); + return retval; + } } } @@ -525,8 +575,12 @@ static int ms_prepare_reset(struct rtsx_chip *chip) return STATUS_FAIL; } } else { - RTSX_WRITE_REG(chip, FPGA_PULL_CTL, - FPGA_MS_PULL_CTL_BIT | 0x20, 0); + retval = rtsx_write_register(chip, FPGA_PULL_CTL, + FPGA_MS_PULL_CTL_BIT | 0x20, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } } if (!chip->ft2_fast_mode) { @@ -553,21 +607,40 @@ static int ms_prepare_reset(struct rtsx_chip *chip) #endif } - RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, MS_OUTPUT_EN); + retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, + MS_OUTPUT_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } if (chip->asic_code) { - RTSX_WRITE_REG(chip, MS_CFG, 0xFF, - SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT | - NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1); + retval = rtsx_write_register(chip, MS_CFG, 0xFF, + SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1); + if (retval) { + rtsx_trace(chip); + return retval; + } } else { - RTSX_WRITE_REG(chip, MS_CFG, 0xFF, - SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT | - NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1); + retval = rtsx_write_register(chip, MS_CFG, 0xFF, + SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1); + if (retval) { + rtsx_trace(chip); + return retval; + } + } + retval = rtsx_write_register(chip, MS_TRANS_CFG, 0xFF, + NO_WAIT_INT | NO_AUTO_READ_INT_REG); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, + MS_STOP | MS_CLR_ERR); + if (retval) { + rtsx_trace(chip); + return retval; } - RTSX_WRITE_REG(chip, MS_TRANS_CFG, - 0xFF, NO_WAIT_INT | NO_AUTO_READ_INT_REG); - RTSX_WRITE_REG(chip, CARD_STOP, - MS_STOP | MS_CLR_ERR, MS_STOP | MS_CLR_ERR); retval = ms_set_init_para(chip); if (retval != STATUS_SUCCESS) { @@ -601,7 +674,11 @@ static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) return STATUS_FAIL; } - RTSX_READ_REG(chip, PPBUF_BASE2 + 2, &val); + retval = rtsx_read_register(chip, PPBUF_BASE2 + 2, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val); if (val != 0x01) { if (val != 0x02) @@ -611,7 +688,11 @@ static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) return STATUS_FAIL; } - RTSX_READ_REG(chip, PPBUF_BASE2 + 4, &val); + retval = rtsx_read_register(chip, PPBUF_BASE2 + 4, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val); if (val != 0) { ms_card->check_ms_flow = 1; @@ -619,10 +700,18 @@ static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) return STATUS_FAIL; } - RTSX_READ_REG(chip, PPBUF_BASE2 + 5, &val); + retval = rtsx_read_register(chip, PPBUF_BASE2 + 5, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val); if (val == 0) { - RTSX_READ_REG(chip, PPBUF_BASE2, &val); + retval = rtsx_read_register(chip, PPBUF_BASE2, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } if (val & WRT_PRTCT) chip->card_wp |= MS_CARD; else @@ -638,7 +727,11 @@ static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) ms_card->ms_type |= TYPE_MSPRO; - RTSX_READ_REG(chip, PPBUF_BASE2 + 3, &val); + retval = rtsx_read_register(chip, PPBUF_BASE2 + 3, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val); if (val == 0) { ms_card->ms_type &= 0x0F; @@ -753,8 +846,12 @@ static int ms_switch_8bit_bus(struct rtsx_chip *chip) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, MS_CFG, 0x98, - MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING); + retval = rtsx_write_register(chip, MS_CFG, 0x98, + MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING); + if (retval) { + rtsx_trace(chip); + return retval; + } ms_card->ms_type |= MS_8BIT; retval = ms_set_init_para(chip); if (retval != STATUS_SUCCESS) { @@ -817,8 +914,17 @@ static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus) } /* Switch MS-PRO into Parallel mode */ - RTSX_WRITE_REG(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4); - RTSX_WRITE_REG(chip, MS_CFG, PUSH_TIME_ODD, PUSH_TIME_ODD); + retval = rtsx_write_register(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, MS_CFG, PUSH_TIME_ODD, + PUSH_TIME_ODD); + if (retval) { + rtsx_trace(chip); + return retval; + } retval = ms_set_init_para(chip); if (retval != STATUS_SUCCESS) { @@ -872,7 +978,11 @@ static int msxc_change_power(struct rtsx_chip *chip, u8 mode) return STATUS_FAIL; } - RTSX_READ_REG(chip, MS_TRANS_CFG, buf); + retval = rtsx_read_register(chip, MS_TRANS_CFG, buf); + if (retval) { + rtsx_trace(chip); + return retval; + } if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR)) { rtsx_trace(chip); return STATUS_FAIL; @@ -1775,7 +1885,11 @@ static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, return STATUS_FAIL; } - RTSX_READ_REG(chip, PPBUF_BASE2, &val); + retval = rtsx_read_register(chip, PPBUF_BASE2, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } if (val & BUF_FULL) { retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT); @@ -2070,7 +2184,11 @@ static int reset_ms(struct rtsx_chip *chip) return STATUS_FAIL; } - RTSX_READ_REG(chip, PPBUF_BASE2, &val); + retval = rtsx_read_register(chip, PPBUF_BASE2, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } if (val & WRT_PRTCT) chip->card_wp |= MS_CARD; else @@ -2238,8 +2356,16 @@ RE_SEARCH: return STATUS_FAIL; } - RTSX_WRITE_REG(chip, PPBUF_BASE2, 0xFF, 0x88); - RTSX_WRITE_REG(chip, PPBUF_BASE2 + 1, 0xFF, 0); + retval = rtsx_write_register(chip, PPBUF_BASE2, 0xFF, 0x88); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, PPBUF_BASE2 + 1, 0xFF, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1, NO_WAIT_INT); @@ -2248,8 +2374,13 @@ RE_SEARCH: return STATUS_FAIL; } - RTSX_WRITE_REG(chip, MS_CFG, 0x58 | MS_NO_CHECK_INT, - MS_BUS_WIDTH_4 | PUSH_TIME_ODD | MS_NO_CHECK_INT); + retval = rtsx_write_register(chip, MS_CFG, + 0x58 | MS_NO_CHECK_INT, + MS_BUS_WIDTH_4 | PUSH_TIME_ODD | MS_NO_CHECK_INT); + if (retval) { + rtsx_trace(chip); + return retval; + } ms_card->ms_type |= MS_4BIT; } @@ -2869,7 +3000,11 @@ static int mspro_rw_multi_sector(struct scsi_cmnd *srb, else trans_mode = MS_TM_AUTO_WRITE; - RTSX_READ_REG(chip, MS_TRANS_CFG, &val); + retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } if (ms_card->seq_mode) { if ((ms_card->pre_dir != srb->sc_data_direction) @@ -3154,7 +3289,11 @@ int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip, return STATUS_FAIL; } - RTSX_READ_REG(chip, MS_TRANS_CFG, &tmp); + retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) { rtsx_trace(chip); @@ -4616,10 +4755,19 @@ int ms_power_off_card3v3(struct rtsx_chip *chip) return STATUS_FAIL; } } else { - RTSX_WRITE_REG(chip, FPGA_PULL_CTL, - FPGA_MS_PULL_CTL_BIT | 0x20, FPGA_MS_PULL_CTL_BIT); + retval = rtsx_write_register(chip, FPGA_PULL_CTL, + FPGA_MS_PULL_CTL_BIT | 0x20, + FPGA_MS_PULL_CTL_BIT); + if (retval) { + rtsx_trace(chip); + return retval; + } + } + retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); + if (retval) { + rtsx_trace(chip); + return retval; } - RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, 0); if (!chip->ft2_fast_mode) { retval = card_power_off(chip, MS_CARD); if (retval != STATUS_SUCCESS) { diff --git a/drivers/staging/rts5208/rtsx_card.c b/drivers/staging/rts5208/rtsx_card.c index d7ca44f61447..437436f5dbdd 100644 --- a/drivers/staging/rts5208/rtsx_card.c +++ b/drivers/staging/rts5208/rtsx_card.c @@ -698,7 +698,11 @@ int switch_ssc_clock(struct rtsx_chip *chip, int clk) } udelay(10); - RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0); + retval = rtsx_write_register(chip, CLK_CTL, CLK_LOW_FREQ, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->cur_clk = clk; @@ -707,6 +711,7 @@ int switch_ssc_clock(struct rtsx_chip *chip, int clk) int switch_normal_clock(struct rtsx_chip *chip, int clk) { + int retval; u8 sel, div, mcu_cnt; int sd_vpclk_phase_reset = 0; @@ -791,23 +796,58 @@ int switch_normal_clock(struct rtsx_chip *chip, int clk) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ); + retval = rtsx_write_register(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ); + if (retval) { + rtsx_trace(chip); + return retval; + } if (sd_vpclk_phase_reset) { - RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); - RTSX_WRITE_REG(chip, SD_VPCLK1_CTL, PHASE_NOT_RESET, 0); + retval = rtsx_write_register(chip, SD_VPCLK0_CTL, + PHASE_NOT_RESET, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, SD_VPCLK1_CTL, + PHASE_NOT_RESET, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } + } + retval = rtsx_write_register(chip, CLK_DIV, 0xFF, + (div << 4) | mcu_cnt); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CLK_SEL, 0xFF, sel); + if (retval) { + rtsx_trace(chip); + return retval; } - RTSX_WRITE_REG(chip, CLK_DIV, 0xFF, (div << 4) | mcu_cnt); - RTSX_WRITE_REG(chip, CLK_SEL, 0xFF, sel); if (sd_vpclk_phase_reset) { udelay(200); - RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, - PHASE_NOT_RESET); - RTSX_WRITE_REG(chip, SD_VPCLK1_CTL, PHASE_NOT_RESET, - PHASE_NOT_RESET); + retval = rtsx_write_register(chip, SD_VPCLK0_CTL, + PHASE_NOT_RESET, PHASE_NOT_RESET); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, SD_VPCLK1_CTL, + PHASE_NOT_RESET, PHASE_NOT_RESET); + if (retval) { + rtsx_trace(chip); + return retval; + } udelay(200); } - RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, 0); + retval = rtsx_write_register(chip, CLK_CTL, 0xFF, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->cur_clk = clk; @@ -842,6 +882,7 @@ void trans_dma_enable(enum dma_data_direction dir, struct rtsx_chip *chip, int enable_card_clock(struct rtsx_chip *chip, u8 card) { + int retval; u8 clk_en = 0; if (card & XD_CARD) @@ -851,13 +892,18 @@ int enable_card_clock(struct rtsx_chip *chip, u8 card) if (card & MS_CARD) clk_en |= MS_CLK_EN; - RTSX_WRITE_REG(chip, CARD_CLK_EN, clk_en, clk_en); + retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, clk_en); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } int disable_card_clock(struct rtsx_chip *chip, u8 card) { + int retval; u8 clk_en = 0; if (card & XD_CARD) @@ -867,7 +913,11 @@ int disable_card_clock(struct rtsx_chip *chip, u8 card) if (card & MS_CARD) clk_en |= MS_CLK_EN; - RTSX_WRITE_REG(chip, CARD_CLK_EN, clk_en, 0); + retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } @@ -912,6 +962,7 @@ int card_power_on(struct rtsx_chip *chip, u8 card) int card_power_off(struct rtsx_chip *chip, u8 card) { + int retval; u8 mask, val; if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) { @@ -922,7 +973,11 @@ int card_power_off(struct rtsx_chip *chip, u8 card) val = SD_POWER_OFF; } - RTSX_WRITE_REG(chip, CARD_PWR_CTL, mask, val); + retval = rtsx_write_register(chip, CARD_PWR_CTL, mask, val); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } @@ -972,6 +1027,7 @@ int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, int card_share_mode(struct rtsx_chip *chip, int card) { + int retval; u8 mask, value; if (CHECK_PID(chip, 0x5208)) { @@ -1005,7 +1061,11 @@ int card_share_mode(struct rtsx_chip *chip, int card) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, CARD_SHARE_MODE, mask, value); + retval = rtsx_write_register(chip, CARD_SHARE_MODE, mask, value); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } @@ -1031,7 +1091,11 @@ int select_card(struct rtsx_chip *chip, int card) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, CARD_SELECT, 0x07, mod); + retval = rtsx_write_register(chip, CARD_SELECT, 0x07, mod); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->cur_card = card; retval = card_share_mode(chip, card); diff --git a/drivers/staging/rts5208/rtsx_card.h b/drivers/staging/rts5208/rtsx_card.h index 75cf5889bda4..8f2cf9a4ec69 100644 --- a/drivers/staging/rts5208/rtsx_card.h +++ b/drivers/staging/rts5208/rtsx_card.h @@ -1061,7 +1061,13 @@ int card_power_off(struct rtsx_chip *chip, u8 card); static inline int card_power_off_all(struct rtsx_chip *chip) { - RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0x0F, 0x0F); + int retval; + + retval = rtsx_write_register(chip, CARD_PWR_CTL, 0x0F, 0x0F); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } diff --git a/drivers/staging/rts5208/rtsx_chip.c b/drivers/staging/rts5208/rtsx_chip.c index a8feee846dd3..0c1716ebc827 100644 --- a/drivers/staging/rts5208/rtsx_chip.c +++ b/drivers/staging/rts5208/rtsx_chip.c @@ -116,22 +116,46 @@ void rtsx_disable_bus_int(struct rtsx_chip *chip) static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip) { + int retval; + if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) { if (chip->asic_code) { - RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, - MS_INS_PU | SD_WP_PU | - SD_CD_PU | SD_CMD_PU); + retval = rtsx_write_register(chip, CARD_PULL_CTL5, + 0xFF, + MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU); + if (retval) { + rtsx_trace(chip); + return retval; + } } else { - RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, - FPGA_SD_PULL_CTL_EN); + retval = rtsx_write_register(chip, FPGA_PULL_CTL, + 0xFF, + FPGA_SD_PULL_CTL_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } + } + retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF, + CARD_SHARE_48_SD); + if (retval) { + rtsx_trace(chip); + return retval; } - RTSX_WRITE_REG(chip, CARD_SHARE_MODE, 0xFF, CARD_SHARE_48_SD); /* Enable SDIO internal clock */ - RTSX_WRITE_REG(chip, 0xFF2C, 0x01, 0x01); + retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01); + if (retval) { + rtsx_trace(chip); + return retval; + } - RTSX_WRITE_REG(chip, SDIO_CTRL, 0xFF, - SDIO_BUS_CTRL | SDIO_CD_CTRL); + retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF, + SDIO_BUS_CTRL | SDIO_CD_CTRL); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->sd_int = 1; chip->sd_io = 1; @@ -151,11 +175,19 @@ static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip) if (chip->driver_first_load) { if (CHECK_PID(chip, 0x5288)) { - RTSX_READ_REG(chip, 0xFE5A, &tmp); + retval = rtsx_read_register(chip, 0xFE5A, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } if (tmp & 0x08) sw_bypass_sd = true; } else if (CHECK_PID(chip, 0x5208)) { - RTSX_READ_REG(chip, 0xFE70, &tmp); + retval = rtsx_read_register(chip, 0xFE70, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } if (tmp & 0x80) sw_bypass_sd = true; } @@ -173,17 +205,37 @@ static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip) if (sw_bypass_sd) { u8 cd_toggle_mask = 0; - RTSX_READ_REG(chip, TLPTISTAT, &tmp); + retval = rtsx_read_register(chip, TLPTISTAT, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } cd_toggle_mask = 0x08; if (tmp & cd_toggle_mask) { /* Disable sdio_bus_auto_switch */ - if (CHECK_PID(chip, 0x5288)) - RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x00); - else if (CHECK_PID(chip, 0x5208)) - RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x00); + if (CHECK_PID(chip, 0x5288)) { + retval = rtsx_write_register(chip, 0xFE5A, + 0x08, 0x00); + if (retval) { + rtsx_trace(chip); + return retval; + } + } else if (CHECK_PID(chip, 0x5208)) { + retval = rtsx_write_register(chip, 0xFE70, + 0x80, 0x00); + if (retval) { + rtsx_trace(chip); + return retval; + } + } - RTSX_WRITE_REG(chip, TLPTISTAT, 0xFF, tmp); + retval = rtsx_write_register(chip, TLPTISTAT, 0xFF, + tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->need_reset |= SD_CARD; } else { @@ -196,8 +248,14 @@ static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip) return STATUS_FAIL; } } else { - RTSX_WRITE_REG(chip, FPGA_PULL_CTL, - FPGA_SD_PULL_CTL_BIT | 0x20, 0); + retval = rtsx_write_register(chip, + FPGA_PULL_CTL, + FPGA_SD_PULL_CTL_BIT | 0x20, + 0); + if (retval) { + rtsx_trace(chip); + return retval; + } } retval = card_share_mode(chip, SD_CARD); if (retval != STATUS_SUCCESS) { @@ -206,16 +264,31 @@ static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip) } /* Enable sdio_bus_auto_switch */ - if (CHECK_PID(chip, 0x5288)) - RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x08); - else if (CHECK_PID(chip, 0x5208)) - RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x80); + if (CHECK_PID(chip, 0x5288)) { + retval = rtsx_write_register(chip, 0xFE5A, + 0x08, 0x08); + if (retval) { + rtsx_trace(chip); + return retval; + } + } else if (CHECK_PID(chip, 0x5208)) { + retval = rtsx_write_register(chip, 0xFE70, + 0x80, 0x80); + if (retval) { + rtsx_trace(chip); + return retval; + } + } chip->chip_insert_with_sdio = 1; chip->sd_io = 1; } } else { - RTSX_WRITE_REG(chip, TLPTISTAT, 0x08, 0x08); + retval = rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->need_reset |= SD_CARD; } @@ -242,8 +315,13 @@ static int rtsx_reset_aspm(struct rtsx_chip *chip) return STATUS_SUCCESS; } - if (CHECK_PID(chip, 0x5208)) - RTSX_WRITE_REG(chip, ASPM_FORCE_CTL, 0xFF, 0x3F); + if (CHECK_PID(chip, 0x5208)) { + ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F); + if (ret) { + rtsx_trace(chip); + return ret; + } + } ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en); if (ret != STATUS_SUCCESS) { rtsx_trace(chip); @@ -276,7 +354,11 @@ static int rtsx_enable_pcie_intr(struct rtsx_chip *chip) } if (chip->phy_debug_mode) { - RTSX_WRITE_REG(chip, CDRESUMECTL, 0x77, 0); + ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0); + if (ret) { + rtsx_trace(chip); + return ret; + } rtsx_disable_bus_int(chip); } else { rtsx_enable_bus_int(chip); @@ -327,47 +409,116 @@ int rtsx_reset_chip(struct rtsx_chip *chip) rtsx_disable_aspm(chip); - RTSX_WRITE_REG(chip, HOST_SLEEP_STATE, 0x03, 0x00); + retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00); + if (retval) { + rtsx_trace(chip); + return retval; + } /* Disable card clock */ - RTSX_WRITE_REG(chip, CARD_CLK_EN, 0x1E, 0); + retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } #ifdef SUPPORT_OCP /* SSC power on, OCD power on */ - if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) - RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, 0); - else - RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, MS_OC_POWER_DOWN); + if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { + retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } + } else { + retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, + MS_OC_POWER_DOWN); + if (retval) { + rtsx_trace(chip); + return retval; + } + } - RTSX_WRITE_REG(chip, OCPPARA1, OCP_TIME_MASK, OCP_TIME_800); - RTSX_WRITE_REG(chip, OCPPARA2, OCP_THD_MASK, OCP_THD_244_946); - RTSX_WRITE_REG(chip, OCPCTL, 0xFF, CARD_OC_INT_EN | CARD_DETECT_EN); + retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK, + OCP_TIME_800); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK, + OCP_THD_244_946); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, OCPCTL, 0xFF, + CARD_OC_INT_EN | CARD_DETECT_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } #else /* OC power down */ - RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, OC_POWER_DOWN); + retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, + OC_POWER_DOWN); + if (retval) { + rtsx_trace(chip); + return retval; + } #endif - if (!CHECK_PID(chip, 0x5288)) - RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0xFF, 0x03); + if (!CHECK_PID(chip, 0x5288)) { + retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03); + if (retval) { + rtsx_trace(chip); + return retval; + } + } /* Turn off LED */ - RTSX_WRITE_REG(chip, CARD_GPIO, 0xFF, 0x03); + retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03); + if (retval) { + rtsx_trace(chip); + return retval; + } /* Reset delink mode */ - RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x0A, 0); + retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } /* Card driving select */ - RTSX_WRITE_REG(chip, CARD_DRIVE_SEL, 0xFF, chip->card_drive_sel); + retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF, + chip->card_drive_sel); + if (retval) { + rtsx_trace(chip); + return retval; + } #ifdef LED_AUTO_BLINK - RTSX_WRITE_REG(chip, CARD_AUTO_BLINK, 0xFF, - LED_BLINK_SPEED | BLINK_EN | LED_GPIO0); + retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF, + LED_BLINK_SPEED | BLINK_EN | LED_GPIO0); + if (retval) { + rtsx_trace(chip); + return retval; + } #endif if (chip->asic_code) { /* Enable SSC Clock */ - RTSX_WRITE_REG(chip, SSC_CTL1, 0xFF, SSC_8X_EN | SSC_SEL_4M); - RTSX_WRITE_REG(chip, SSC_CTL2, 0xFF, 0x12); + retval = rtsx_write_register(chip, SSC_CTL1, 0xFF, + SSC_8X_EN | SSC_SEL_4M); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12); + if (retval) { + rtsx_trace(chip); + return retval; + } } /* Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0) @@ -377,7 +528,11 @@ int rtsx_reset_chip(struct rtsx_chip *chip) bit[5] u_mac_phy_rst_n_dbg rst_value = 1 bit[4] u_non_sticky_rst_n_dbg rst_value = 0 */ - RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x16, 0x10); + retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10); + if (retval) { + rtsx_trace(chip); + return retval; + } /* Enable ASPM */ if (chip->aspm_l0s_l1_en) { @@ -433,9 +588,18 @@ int rtsx_reset_chip(struct rtsx_chip *chip) } } - RTSX_WRITE_REG(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT); + retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, + LINK_RDY_INT); + if (retval) { + rtsx_trace(chip); + return retval; + } - RTSX_WRITE_REG(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80); + retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80); + if (retval) { + rtsx_trace(chip); + return retval; + } retval = rtsx_enable_pcie_intr(chip); if (retval != STATUS_SUCCESS) { @@ -470,8 +634,12 @@ int rtsx_reset_chip(struct rtsx_chip *chip) } else { chip->sd_io = 0; - RTSX_WRITE_REG(chip, SDIO_CTRL, SDIO_BUS_CTRL | SDIO_CD_CTRL, - 0); + retval = rtsx_write_register(chip, SDIO_CTRL, + SDIO_BUS_CTRL | SDIO_CD_CTRL, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } } nextcard: @@ -479,30 +647,68 @@ nextcard: chip->need_reset |= XD_CARD; if (chip->int_reg & MS_EXIST) chip->need_reset |= MS_CARD; - if (chip->int_reg & CARD_EXIST) - RTSX_WRITE_REG(chip, SSC_CTL1, SSC_RSTB, SSC_RSTB); + if (chip->int_reg & CARD_EXIST) { + retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB, + SSC_RSTB); + if (retval) { + rtsx_trace(chip); + return retval; + } + } dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__, (unsigned int)(chip->need_reset)); - RTSX_WRITE_REG(chip, RCCTL, 0x01, 0x00); + retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00); + if (retval) { + rtsx_trace(chip); + return retval; + } if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) { /* Turn off main power when entering S3/S4 state */ - RTSX_WRITE_REG(chip, MAIN_PWR_OFF_CTL, 0x03, 0x03); + retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03, + 0x03); + if (retval) { + rtsx_trace(chip); + return retval; + } } if (chip->remote_wakeup_en && !chip->auto_delink_en) { - RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x07); - if (chip->aux_pwr_exist) - RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x33); + retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07); + if (retval) { + rtsx_trace(chip); + return retval; + } + if (chip->aux_pwr_exist) { + retval = rtsx_write_register(chip, PME_FORCE_CTL, + 0xFF, 0x33); + if (retval) { + rtsx_trace(chip); + return retval; + } + } } else { - RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x04); - RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x30); + retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30); + if (retval) { + rtsx_trace(chip); + return retval; + } } - if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) - RTSX_WRITE_REG(chip, PETXCFG, 0x1C, 0x14); + if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) { + retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14); + if (retval) { + rtsx_trace(chip); + return retval; + } + } if (chip->asic_code && CHECK_PID(chip, 0x5208)) { retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2); @@ -513,11 +719,19 @@ nextcard: } if (chip->ft2_fast_mode) { - RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, - MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON); + retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF, + MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON); + if (retval) { + rtsx_trace(chip); + return retval; + } udelay(chip->pmos_pwr_on_interval); - RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, - MS_POWER_ON | SD_POWER_ON); + retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF, + MS_POWER_ON | SD_POWER_ON); + if (retval) { + rtsx_trace(chip); + return retval; + } wait_timeout(200); } @@ -570,8 +784,16 @@ static int rts5208_init(struct rtsx_chip *chip) u16 reg = 0; u8 val = 0; - RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03); - RTSX_READ_REG(chip, CLK_SEL, &val); + retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_read_register(chip, CLK_SEL, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->asic_code = val == 0 ? 1 : 0; if (chip->asic_code) { @@ -587,16 +809,28 @@ static int rts5208_init(struct rtsx_chip *chip) chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0; } else { - RTSX_READ_REG(chip, 0xFE80, &val); + retval = rtsx_read_register(chip, 0xFE80, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->ic_version = val; chip->phy_debug_mode = 0; } - RTSX_READ_REG(chip, PDINFO, &val); + retval = rtsx_read_register(chip, PDINFO, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val); chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0; - RTSX_READ_REG(chip, 0xFE50, &val); + retval = rtsx_read_register(chip, 0xFE50, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->hw_bypass_sd = val & 0x01 ? 1 : 0; rtsx_read_config_byte(chip, 0x0E, &val); @@ -606,7 +840,11 @@ static int rts5208_init(struct rtsx_chip *chip) CLR_SDIO_EXIST(chip); if (chip->use_hw_setting) { - RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val); + retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->auto_delink_en = val & 0x80 ? 1 : 0; } @@ -619,22 +857,42 @@ static int rts5288_init(struct rtsx_chip *chip) u8 val = 0, max_func; u32 lval = 0; - RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03); - RTSX_READ_REG(chip, CLK_SEL, &val); + retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_read_register(chip, CLK_SEL, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->asic_code = val == 0 ? 1 : 0; chip->ic_version = 0; chip->phy_debug_mode = 0; - RTSX_READ_REG(chip, PDINFO, &val); + retval = rtsx_read_register(chip, PDINFO, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val); chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0; - RTSX_READ_REG(chip, CARD_SHARE_MODE, &val); + retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val); chip->baro_pkg = val & 0x04 ? QFN : LQFP; - RTSX_READ_REG(chip, 0xFE5A, &val); + retval = rtsx_read_register(chip, 0xFE5A, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->hw_bypass_sd = val & 0x10 ? 1 : 0; retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval); @@ -651,7 +909,11 @@ static int rts5288_init(struct rtsx_chip *chip) CLR_SDIO_EXIST(chip); if (chip->use_hw_setting) { - RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val); + retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->auto_delink_en = val & 0x80 ? 1 : 0; if (CHECK_BARO_PKG(chip, LQFP)) @@ -730,9 +992,17 @@ int rtsx_init_chip(struct rtsx_chip *chip) if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0)) chip->mmc_ddr_tx_phase = 0; - RTSX_WRITE_REG(chip, FPDCTL, SSC_POWER_DOWN, 0); + retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } wait_timeout(200); - RTSX_WRITE_REG(chip, CLK_DIV, 0x07, 0x07); + retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n", chip->use_hw_setting); @@ -1241,13 +1511,19 @@ int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data) int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, u32 val) { + int retval; u8 mode = 0, tmp; int i; for (i = 0; i < 4; i++) { if (mask & 0xFF) { - RTSX_WRITE_REG(chip, CFGDATA0 + i, - 0xFF, (u8)(val & mask & 0xFF)); + retval = rtsx_write_register(chip, CFGDATA0 + i, + 0xFF, + (u8)(val & mask & 0xFF)); + if (retval) { + rtsx_trace(chip); + return retval; + } mode |= (1 << i); } mask >>= 8; @@ -1255,14 +1531,31 @@ int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, } if (mode) { - RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr); - RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8)); + retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CFGADDR1, 0xFF, + (u8)(addr >> 8)); + if (retval) { + rtsx_trace(chip); + return retval; + } - RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, - 0x80 | mode | ((func_no & 0x03) << 4)); + retval = rtsx_write_register(chip, CFGRWCTL, 0xFF, + 0x80 | mode | ((func_no & 0x03) << 4)); + if (retval) { + rtsx_trace(chip); + return retval; + } for (i = 0; i < MAX_RW_REG_CNT; i++) { - RTSX_READ_REG(chip, CFGRWCTL, &tmp); + retval = rtsx_read_register(chip, CFGRWCTL, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } if ((tmp & 0x80) == 0) break; } @@ -1273,22 +1566,44 @@ int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val) { + int retval; int i; u8 tmp; u32 data = 0; - RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr); - RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8)); - RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, 0x80 | ((func_no & 0x03) << 4)); + retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CFGADDR1, 0xFF, (u8)(addr >> 8)); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CFGRWCTL, 0xFF, + 0x80 | ((func_no & 0x03) << 4)); + if (retval) { + rtsx_trace(chip); + return retval; + } for (i = 0; i < MAX_RW_REG_CNT; i++) { - RTSX_READ_REG(chip, CFGRWCTL, &tmp); + retval = rtsx_read_register(chip, CFGRWCTL, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } if ((tmp & 0x80) == 0) break; } for (i = 0; i < 4; i++) { - RTSX_READ_REG(chip, CFGDATA0 + i, &tmp); + retval = rtsx_read_register(chip, CFGDATA0 + i, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } data |= (u32)tmp << (i * 8); } @@ -1415,17 +1730,38 @@ int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val) { + int retval; bool finished = false; int i; u8 tmp; - RTSX_WRITE_REG(chip, PHYDATA0, 0xFF, (u8)val); - RTSX_WRITE_REG(chip, PHYDATA1, 0xFF, (u8)(val >> 8)); - RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr); - RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x81); + retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8)); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x81); + if (retval) { + rtsx_trace(chip); + return retval; + } for (i = 0; i < 100000; i++) { - RTSX_READ_REG(chip, PHYRWCTL, &tmp); + retval = rtsx_read_register(chip, PHYRWCTL, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } if (!(tmp & 0x80)) { finished = true; break; @@ -1442,16 +1778,29 @@ int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val) int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val) { + int retval; bool finished = false; int i; u16 data = 0; u8 tmp; - RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr); - RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x80); + retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x80); + if (retval) { + rtsx_trace(chip); + return retval; + } for (i = 0; i < 100000; i++) { - RTSX_READ_REG(chip, PHYRWCTL, &tmp); + retval = rtsx_read_register(chip, PHYRWCTL, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } if (!(tmp & 0x80)) { finished = true; break; @@ -1463,9 +1812,17 @@ int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val) return STATUS_FAIL; } - RTSX_READ_REG(chip, PHYDATA0, &tmp); + retval = rtsx_read_register(chip, PHYDATA0, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } data = tmp; - RTSX_READ_REG(chip, PHYDATA1, &tmp); + retval = rtsx_read_register(chip, PHYDATA1, &tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } data |= (u16)tmp << 8; if (val) @@ -1476,13 +1833,22 @@ int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val) int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val) { + int retval; int i; u8 data = 0; - RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0x80|addr); + retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 0x80 | addr); + if (retval) { + rtsx_trace(chip); + return retval; + } for (i = 0; i < 100; i++) { - RTSX_READ_REG(chip, EFUSE_CTRL, &data); + retval = rtsx_read_register(chip, EFUSE_CTRL, &data); + if (retval) { + rtsx_trace(chip); + return retval; + } if (!(data & 0x80)) break; udelay(1); @@ -1493,7 +1859,11 @@ int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val) return STATUS_TIMEDOUT; } - RTSX_READ_REG(chip, EFUSE_DATA, &data); + retval = rtsx_read_register(chip, EFUSE_DATA, &data); + if (retval) { + rtsx_trace(chip); + return retval; + } if (val) *val = data; @@ -1502,6 +1872,7 @@ int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val) int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val) { + int retval; int i, j; u8 data = 0, tmp = 0xFF; @@ -1512,11 +1883,24 @@ int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val) tmp &= (~(u8)(1 << i)); dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr); - RTSX_WRITE_REG(chip, EFUSE_DATA, 0xFF, tmp); - RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0xA0|addr); + retval = rtsx_write_register(chip, EFUSE_DATA, 0xFF, tmp); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, + 0xA0 | addr); + if (retval) { + rtsx_trace(chip); + return retval; + } for (j = 0; j < 100; j++) { - RTSX_READ_REG(chip, EFUSE_CTRL, &data); + retval = rtsx_read_register(chip, EFUSE_CTRL, &data); + if (retval) { + rtsx_trace(chip); + return retval; + } if (!(data & 0x80)) break; wait_timeout(3); @@ -1581,9 +1965,14 @@ int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit) int rtsx_check_link_ready(struct rtsx_chip *chip) { + int retval; u8 val; - RTSX_READ_REG(chip, IRQSTAT0, &val); + retval = rtsx_read_register(chip, IRQSTAT0, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "IRQSTAT0: 0x%x\n", val); if (val & LINK_RDY_INT) { diff --git a/drivers/staging/rts5208/rtsx_chip.h b/drivers/staging/rts5208/rtsx_chip.h index 93fd7b286f49..c295b1eedb44 100644 --- a/drivers/staging/rts5208/rtsx_chip.h +++ b/drivers/staging/rts5208/rtsx_chip.h @@ -988,22 +988,4 @@ int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len); int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len); int rtsx_check_chip_exist(struct rtsx_chip *chip); -#define RTSX_WRITE_REG(chip, addr, mask, data) \ -do { \ - int retval = rtsx_write_register(chip, addr, mask, data); \ - if (retval != STATUS_SUCCESS) { \ - rtsx_trace(chip); \ - return retval; \ - } \ -} while (0) - -#define RTSX_READ_REG(chip, addr, data) \ -do { \ - int retval = rtsx_read_register(chip, addr, data); \ - if (retval != STATUS_SUCCESS) { \ - rtsx_trace(chip); \ - return retval; \ - } \ -} while (0) - #endif /* __REALTEK_RTSX_CHIP_H */ diff --git a/drivers/staging/rts5208/sd.c b/drivers/staging/rts5208/sd.c index 0eee67642e45..a8d657bb5c1b 100644 --- a/drivers/staging/rts5208/sd.c +++ b/drivers/staging/rts5208/sd.c @@ -105,9 +105,14 @@ static void sd_init_reg_addr(struct rtsx_chip *chip) static int sd_check_data0_status(struct rtsx_chip *chip) { + int retval; u8 stat; - RTSX_READ_REG(chip, REG_SD_STAT1, &stat); + retval = rtsx_read_register(chip, REG_SD_STAT1, &stat); + if (retval) { + rtsx_trace(chip); + return retval; + } if (!(stat & SD_DAT0_STATUS)) { sd_set_err_code(chip, SD_BUSY); @@ -529,8 +534,8 @@ static int sd_check_csd(struct rtsx_chip *chip, char check_wp) static int sd_set_sample_push_timing(struct rtsx_chip *chip) { + int retval; struct sd_info *sd_card = &(chip->sd_card); - u8 val = 0; if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY) @@ -558,7 +563,11 @@ static int sd_set_sample_push_timing(struct rtsx_chip *chip) val |= 0x08; } - RTSX_WRITE_REG(chip, REG_SD_CFG1, 0x1C, val); + retval = rtsx_write_register(chip, REG_SD_CFG1, 0x1C, val); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } @@ -607,6 +616,7 @@ static void sd_choose_proper_clock(struct rtsx_chip *chip) static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div) { + int retval; u8 mask = 0, val = 0; mask = 0x60; @@ -617,7 +627,11 @@ static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div) else if (clk_div == SD_CLK_DIVIDE_256) val = 0x20; - RTSX_WRITE_REG(chip, REG_SD_CFG1, mask, val); + retval = rtsx_write_register(chip, REG_SD_CFG1, mask, val); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } @@ -740,7 +754,12 @@ static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage) return STATUS_FAIL; } } else { - RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, 0); + retval = rtsx_write_register(chip, SD_PAD_CTL, + SD_IO_USING_1V8, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } } } else if (voltage == SD_IO_1V8) { if (chip->asic_code) { @@ -752,8 +771,13 @@ static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage) return STATUS_FAIL; } } else { - RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, - SD_IO_USING_1V8); + retval = rtsx_write_register(chip, SD_PAD_CTL, + SD_IO_USING_1V8, + SD_IO_USING_1V8); + if (retval) { + rtsx_trace(chip); + return retval; + } } } else { rtsx_trace(chip); @@ -768,8 +792,13 @@ static int sd_voltage_switch(struct rtsx_chip *chip) int retval; u8 stat; - RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, - SD_CLK_TOGGLE_EN); + retval = rtsx_write_register(chip, SD_BUS_STAT, + SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, + SD_CLK_TOGGLE_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, NULL, 0); @@ -780,14 +809,23 @@ static int sd_voltage_switch(struct rtsx_chip *chip) udelay(chip->sd_voltage_switch_delay); - RTSX_READ_REG(chip, SD_BUS_STAT, &stat); + retval = rtsx_read_register(chip, SD_BUS_STAT, &stat); + if (retval) { + rtsx_trace(chip); + return retval; + } if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | SD_DAT1_STATUS | SD_DAT0_STATUS)) { rtsx_trace(chip); return STATUS_FAIL; } - RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_FORCE_STOP); + retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF, + SD_CLK_FORCE_STOP); + if (retval) { + rtsx_trace(chip); + return retval; + } retval = sd_change_bank_voltage(chip, SD_IO_1V8); if (retval != STATUS_SUCCESS) { rtsx_trace(chip); @@ -796,10 +834,19 @@ static int sd_voltage_switch(struct rtsx_chip *chip) wait_timeout(50); - RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); + retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF, + SD_CLK_TOGGLE_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } wait_timeout(10); - RTSX_READ_REG(chip, SD_BUS_STAT, &stat); + retval = rtsx_read_register(chip, SD_BUS_STAT, &stat); + if (retval) { + rtsx_trace(chip); + return retval; + } if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | SD_DAT1_STATUS | SD_DAT0_STATUS)) != (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | @@ -812,20 +859,44 @@ static int sd_voltage_switch(struct rtsx_chip *chip) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, - 0); + retval = rtsx_write_register(chip, SD_BUS_STAT, + SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir) { + int retval; + if (tune_dir == TUNE_RX) { - RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_RX); - RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RX); + retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, + DCM_RESET | DCM_RX); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_RX); + if (retval) { + rtsx_trace(chip); + return retval; + } } else { - RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_TX); - RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_TX); + retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, + DCM_RESET | DCM_TX); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_TX); + if (retval) { + rtsx_trace(chip); + return retval; + } } return STATUS_SUCCESS; @@ -853,12 +924,35 @@ static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir) } if (chip->asic_code) { - RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK); - RTSX_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point); - RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); - RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, - PHASE_NOT_RESET); - RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0); + retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, + CHANGE_CLK); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, SD_VP_CTL, 0x1F, + sample_point); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, SD_VPCLK0_CTL, + PHASE_NOT_RESET, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, SD_VPCLK0_CTL, + PHASE_NOT_RESET, PHASE_NOT_RESET); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } } else { rtsx_read_register(chip, SD_VP_CTL, &val); dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val); @@ -866,16 +960,34 @@ static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir) dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val); if (ddr_rx) { - RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, - PHASE_CHANGE); + retval = rtsx_write_register(chip, SD_VP_CTL, + PHASE_CHANGE, + PHASE_CHANGE); + if (retval) { + rtsx_trace(chip); + return retval; + } udelay(50); - RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF, - PHASE_CHANGE | PHASE_NOT_RESET | sample_point); + retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF, + PHASE_CHANGE | PHASE_NOT_RESET | sample_point); + if (retval) { + rtsx_trace(chip); + return retval; + } } else { - RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK); + retval = rtsx_write_register(chip, CLK_CTL, + CHANGE_CLK, CHANGE_CLK); + if (retval) { + rtsx_trace(chip); + return retval; + } udelay(50); - RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF, - PHASE_NOT_RESET | sample_point); + retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF, + PHASE_NOT_RESET | sample_point); + if (retval) { + rtsx_trace(chip); + return retval; + } } udelay(100); @@ -901,16 +1013,36 @@ static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir) goto Fail; } - RTSX_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0); - if (ddr_rx) - RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0); - else - RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0); + retval = rtsx_write_register(chip, SD_DCMPS_CTL, + DCMPS_CHANGE, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } + if (ddr_rx) { + retval = rtsx_write_register(chip, SD_VP_CTL, + PHASE_CHANGE, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } + } else { + retval = rtsx_write_register(chip, CLK_CTL, + CHANGE_CLK, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } + } udelay(50); } - RTSX_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); + retval = rtsx_write_register(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; @@ -1160,10 +1292,20 @@ static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode, } if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) { - RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, - chip->sd_800mA_ocp_thd); - RTSX_WRITE_REG(chip, CARD_PWR_CTL, PMOS_STRG_MASK, - PMOS_STRG_800mA); + retval = rtsx_write_register(chip, OCPPARA2, + SD_OCP_THD_MASK, + chip->sd_800mA_ocp_thd); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PWR_CTL, + PMOS_STRG_MASK, + PMOS_STRG_800mA); + if (retval) { + rtsx_trace(chip); + return retval; + } } } @@ -1210,7 +1352,11 @@ static int sd_check_switch(struct rtsx_chip *chip, break; } - RTSX_READ_REG(chip, SD_STAT1, &stat); + retval = rtsx_read_register(chip, SD_STAT1, &stat); + if (retval) { + rtsx_trace(chip); + return retval; + } if (stat & SD_CRC16_ERR) { dev_dbg(rtsx_dev(chip), "SD CRC16 error when switching mode\n"); rtsx_trace(chip); @@ -1328,7 +1474,12 @@ static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width) } if (CHK_SD_DDR50(sd_card)) { - RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0x04); + retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06, + 0x04); + if (retval) { + rtsx_trace(chip); + return retval; + } retval = sd_set_sample_push_timing(chip); if (retval != STATUS_SUCCESS) { rtsx_trace(chip); @@ -1396,8 +1547,13 @@ static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width) retval); } - if (CHK_SD_DDR50(sd_card)) - RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0); + if (CHK_SD_DDR50(sd_card)) { + retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } + } return STATUS_SUCCESS; } @@ -1409,7 +1565,11 @@ static int sd_wait_data_idle(struct rtsx_chip *chip) u8 val = 0; for (i = 0; i < 100; i++) { - RTSX_READ_REG(chip, SD_DATA_STATE, &val); + retval = rtsx_read_register(chip, SD_DATA_STATE, &val); + if (retval) { + rtsx_trace(chip); + return retval; + } if (val & SD_DATA_IDLE) { retval = STATUS_SUCCESS; break; @@ -1542,8 +1702,12 @@ static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, - SD_RSP_80CLK_TIMEOUT_EN); + retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, + SD_RSP_80CLK_TIMEOUT_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); @@ -1556,7 +1720,12 @@ static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point) } } - RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); + retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, + 0); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } @@ -1590,8 +1759,12 @@ static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, - SD_RSP_80CLK_TIMEOUT_EN); + retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, + SD_RSP_80CLK_TIMEOUT_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } cmd[0] = 0x40 | PROGRAM_CSD; cmd[1] = 0; @@ -1608,7 +1781,12 @@ static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); + retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, + 0); + if (retval) { + rtsx_trace(chip); + return retval; + } sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); @@ -1804,8 +1982,12 @@ static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip) u32 phase_map; u8 final_phase; - RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, - SD_RSP_80CLK_TIMEOUT_EN); + retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, + SD_RSP_80CLK_TIMEOUT_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } phase_map = 0; for (i = MAX_PHASE; i >= 0; i--) { @@ -1829,7 +2011,12 @@ static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip) phase_map |= 1 << i; } - RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); + retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, + 0); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase_map = 0x%08x\n", phase_map); @@ -2073,10 +2260,18 @@ static int sd_prepare_reset(struct rtsx_chip *chip) return retval; } - RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF, 0x40); + retval = rtsx_write_register(chip, REG_SD_CFG1, 0xFF, 0x40); + if (retval) { + rtsx_trace(chip); + return retval; + } - RTSX_WRITE_REG(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, - SD_STOP | SD_CLR_ERR); + retval = rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, + SD_STOP | SD_CLR_ERR); + if (retval) { + rtsx_trace(chip); + return retval; + } retval = select_card(chip, SD_CARD); if (retval != STATUS_SUCCESS) { @@ -2089,24 +2284,71 @@ static int sd_prepare_reset(struct rtsx_chip *chip) static int sd_pull_ctl_disable(struct rtsx_chip *chip) { + int retval; + if (CHECK_PID(chip, 0x5208)) { - RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, - XD_D3_PD | SD_D7_PD | SD_CLK_PD | SD_D5_PD); - RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, - SD_D6_PD | SD_D0_PD | SD_D1_PD | XD_D5_PD); - RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, - SD_D4_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); - RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, - XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); - RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, - MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); - RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD); + retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, + XD_D3_PD | SD_D7_PD | SD_CLK_PD | SD_D5_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, + SD_D6_PD | SD_D0_PD | SD_D1_PD | XD_D5_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, + SD_D4_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, + XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, + MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, + MS_D5_PD | MS_D4_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } } else if (CHECK_PID(chip, 0x5288)) { if (CHECK_BARO_PKG(chip, QFN)) { - RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55); - RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55); - RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B); - RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69); + retval = rtsx_write_register(chip, CARD_PULL_CTL1, + 0xFF, 0x55); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL2, + 0xFF, 0x55); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL3, + 0xFF, 0x4B); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL4, + 0xFF, 0x69); + if (retval) { + rtsx_trace(chip); + return retval; + } } } @@ -2180,8 +2422,12 @@ static int sd_init_power(struct rtsx_chip *chip) return STATUS_FAIL; } } else { - RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20, - 0); + retval = rtsx_write_register(chip, FPGA_PULL_CTL, + FPGA_SD_PULL_CTL_BIT | 0x20, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } } if (!chip->ft2_fast_mode) { @@ -2203,16 +2449,31 @@ static int sd_init_power(struct rtsx_chip *chip) #endif } - RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); + retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, + SD_OUTPUT_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } static int sd_dummy_clock(struct rtsx_chip *chip) { - RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0x01); + int retval; + + retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0x01); + if (retval) { + rtsx_trace(chip); + return retval; + } wait_timeout(5); - RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0); + retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } @@ -2622,8 +2883,12 @@ SD_UNLOCK_ENTRY: if (!sd20_mode && CHK_SD30_SPEED(sd_card)) { int read_lba0 = 1; - RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, - chip->sd30_drive_sel_1v8); + retval = rtsx_write_register(chip, SD30_DRIVE_SEL, 0x07, + chip->sd30_drive_sel_1v8); + if (retval) { + rtsx_trace(chip); + return retval; + } retval = sd_set_init_para(chip); if (retval != STATUS_SUCCESS) { @@ -2693,8 +2958,18 @@ SD_UNLOCK_ENTRY: #ifdef SUPPORT_SD_LOCK if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) { - RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02); - RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00); + retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF, + 0x02); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF, + 0x00); + if (retval) { + rtsx_trace(chip); + return retval; + } } #endif @@ -3149,8 +3424,18 @@ MMC_UNLOCK_ENTRY: #ifdef SUPPORT_SD_LOCK if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) { - RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02); - RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00); + retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF, + 0x02); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF, + 0x00); + if (retval) { + rtsx_trace(chip); + return retval; + } } #endif @@ -3251,8 +3536,16 @@ int reset_sd_card(struct rtsx_chip *chip) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); - RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); + retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity; @@ -3309,8 +3602,16 @@ static int reset_mmc_only(struct rtsx_chip *chip) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); - RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); + retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); + if (retval) { + rtsx_trace(chip); + return retval; + } chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity; @@ -4950,7 +5251,11 @@ int sd_power_off_card3v3(struct rtsx_chip *chip) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, 0); + retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } if (!chip->ft2_fast_mode) { retval = card_power_off(chip, SD_CARD); @@ -4969,8 +5274,13 @@ int sd_power_off_card3v3(struct rtsx_chip *chip) return STATUS_FAIL; } } else { - RTSX_WRITE_REG(chip, FPGA_PULL_CTL, - FPGA_SD_PULL_CTL_BIT | 0x20, FPGA_SD_PULL_CTL_BIT); + retval = rtsx_write_register(chip, FPGA_PULL_CTL, + FPGA_SD_PULL_CTL_BIT | 0x20, + FPGA_SD_PULL_CTL_BIT); + if (retval) { + rtsx_trace(chip); + return retval; + } } return STATUS_SUCCESS; diff --git a/drivers/staging/rts5208/spi.c b/drivers/staging/rts5208/spi.c index d3ac6c0b11b5..e67e7ecc2cbd 100644 --- a/drivers/staging/rts5208/spi.c +++ b/drivers/staging/rts5208/spi.c @@ -36,10 +36,20 @@ static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code) static int spi_init(struct rtsx_chip *chip) { - RTSX_WRITE_REG(chip, SPI_CONTROL, 0xFF, - CS_POLARITY_LOW | DTO_MSB_FIRST | SPI_MASTER | SPI_MODE0 | - SPI_AUTO); - RTSX_WRITE_REG(chip, SPI_TCTL, EDO_TIMING_MASK, SAMPLE_DELAY_HALF); + int retval; + + retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, + CS_POLARITY_LOW | DTO_MSB_FIRST | SPI_MASTER | SPI_MODE0 | SPI_AUTO); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, + SAMPLE_DELAY_HALF); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } @@ -49,8 +59,18 @@ static int spi_set_init_para(struct rtsx_chip *chip) struct spi_info *spi = &(chip->spi); int retval; - RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER1, 0xFF, (u8)(spi->clk_div >> 8)); - RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER0, 0xFF, (u8)(spi->clk_div)); + retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, + (u8)(spi->clk_div >> 8)); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, + (u8)(spi->clk_div)); + if (retval) { + rtsx_trace(chip); + return retval; + } retval = switch_clock(chip, spi->spi_clock); if (retval != STATUS_SUCCESS) { @@ -64,8 +84,18 @@ static int spi_set_init_para(struct rtsx_chip *chip) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, CARD_CLK_EN, SPI_CLK_EN, SPI_CLK_EN); - RTSX_WRITE_REG(chip, CARD_OE, SPI_OUTPUT_EN, SPI_OUTPUT_EN); + retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, + SPI_CLK_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, + SPI_OUTPUT_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } wait_timeout(10); @@ -228,8 +258,16 @@ static int spi_init_eeprom(struct rtsx_chip *chip) else clk = CLK_30; - RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00); - RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27); + retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27); + if (retval) { + rtsx_trace(chip); + return retval; + } retval = switch_clock(chip, clk); if (retval != STATUS_SUCCESS) { @@ -243,14 +281,33 @@ static int spi_init_eeprom(struct rtsx_chip *chip) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, CARD_CLK_EN, SPI_CLK_EN, SPI_CLK_EN); - RTSX_WRITE_REG(chip, CARD_OE, SPI_OUTPUT_EN, SPI_OUTPUT_EN); + retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, + SPI_CLK_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, + SPI_OUTPUT_EN); + if (retval) { + rtsx_trace(chip); + return retval; + } wait_timeout(10); - RTSX_WRITE_REG(chip, SPI_CONTROL, 0xFF, - CS_POLARITY_HIGH | SPI_EEPROM_AUTO); - RTSX_WRITE_REG(chip, SPI_TCTL, EDO_TIMING_MASK, SAMPLE_DELAY_HALF); + retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, + CS_POLARITY_HIGH | SPI_EEPROM_AUTO); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, + SAMPLE_DELAY_HALF); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } @@ -310,7 +367,11 @@ int spi_erase_eeprom_chip(struct rtsx_chip *chip) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01); + retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } @@ -350,7 +411,11 @@ int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01); + retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } @@ -388,12 +453,20 @@ int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val) } wait_timeout(5); - RTSX_READ_REG(chip, SPI_DATA, &data); + retval = rtsx_read_register(chip, SPI_DATA, &data); + if (retval) { + rtsx_trace(chip); + return retval; + } if (val) *val = data; - RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01); + retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } @@ -434,7 +507,11 @@ int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01); + retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); + if (retval) { + rtsx_trace(chip); + return retval; + } return STATUS_SUCCESS; } diff --git a/drivers/staging/rts5208/xd.c b/drivers/staging/rts5208/xd.c index 2afa6021c33b..8fd108e50509 100644 --- a/drivers/staging/rts5208/xd.c +++ b/drivers/staging/rts5208/xd.c @@ -252,14 +252,22 @@ static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, return STATUS_FAIL; } - RTSX_READ_REG(chip, XD_PAGE_STATUS, ®); + retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®); + if (retval) { + rtsx_trace(chip); + return retval; + } if (reg != XD_GPG) { rtsx_clear_xd_error(chip); rtsx_trace(chip); return STATUS_FAIL; } - RTSX_READ_REG(chip, XD_CTL, ®); + retval = rtsx_read_register(chip, XD_CTL, ®); + if (retval) { + rtsx_trace(chip); + return retval; + } if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) { retval = xd_read_data_from_ppb(chip, 0, buf, buf_len); if (retval != STATUS_SUCCESS) { @@ -269,8 +277,18 @@ static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, if (reg & XD_ECC1_ERROR) { u8 ecc_bit, ecc_byte; - RTSX_READ_REG(chip, XD_ECC_BIT1, &ecc_bit); - RTSX_READ_REG(chip, XD_ECC_BYTE1, &ecc_byte); + retval = rtsx_read_register(chip, XD_ECC_BIT1, + &ecc_bit); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_read_register(chip, XD_ECC_BYTE1, + &ecc_byte); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n", ecc_bit, ecc_byte); @@ -293,8 +311,18 @@ static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, if (reg & XD_ECC2_ERROR) { u8 ecc_bit, ecc_byte; - RTSX_READ_REG(chip, XD_ECC_BIT2, &ecc_bit); - RTSX_READ_REG(chip, XD_ECC_BYTE2, &ecc_byte); + retval = rtsx_read_register(chip, XD_ECC_BIT2, + &ecc_bit); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_read_register(chip, XD_ECC_BYTE2, + &ecc_byte); + if (retval) { + rtsx_trace(chip); + return retval; + } dev_dbg(rtsx_dev(chip), "ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n", ecc_bit, ecc_byte); @@ -385,24 +413,71 @@ static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip) static int xd_pull_ctl_disable(struct rtsx_chip *chip) { + int retval; + if (CHECK_PID(chip, 0x5208)) { - RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, - XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); - RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, - XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); - RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, - XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); - RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, - XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD); - RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, - MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); - RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD); + retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, + XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, + XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, + XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, + XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, + MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, + MS_D5_PD | MS_D4_PD); + if (retval) { + rtsx_trace(chip); + return retval; + } } else if (CHECK_PID(chip, 0x5288)) { if (CHECK_BARO_PKG(chip, QFN)) { - RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55); - RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55); - RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B); - RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69); + retval = rtsx_write_register(chip, CARD_PULL_CTL1, + 0xFF, 0x55); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL2, + 0xFF, 0x55); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL3, + 0xFF, 0x4B); + if (retval) { + rtsx_trace(chip); + return retval; + } + retval = rtsx_write_register(chip, CARD_PULL_CTL4, + 0xFF, 0x69); + if (retval) { + rtsx_trace(chip); + return retval; + } } } @@ -1144,7 +1219,12 @@ static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, XD_CLR_BAD_NEWBLK(xd_card); - RTSX_WRITE_REG(chip, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); + retval = rtsx_write_register(chip, CARD_DATA_SOURCE, 0x01, + PINGPONG_BUFFER); + if (retval) { + rtsx_trace(chip); + return retval; + } for (i = start_page; i < end_page; i++) { if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { @@ -1619,12 +1699,20 @@ static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk, return STATUS_SUCCESS; Fail: - RTSX_READ_REG(chip, XD_PAGE_STATUS, ®_val); + retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®_val); + if (retval) { + rtsx_trace(chip); + return retval; + } if (reg_val != XD_GPG) xd_set_err_code(chip, XD_PRG_ERROR); - RTSX_READ_REG(chip, XD_CTL, ®_val); + retval = rtsx_read_register(chip, XD_CTL, ®_val); + if (retval) { + rtsx_trace(chip); + return retval; + } if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) @@ -1847,7 +1935,11 @@ static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk, return STATUS_SUCCESS; Fail: - RTSX_READ_REG(chip, XD_DAT, ®_val); + retval = rtsx_read_register(chip, XD_DAT, ®_val); + if (retval) { + rtsx_trace(chip); + return retval; + } if (reg_val & PROGRAM_ERROR) { xd_set_err_code(chip, XD_PRG_ERROR); xd_mark_bad_block(chip, new_blk); @@ -2197,7 +2289,11 @@ int xd_power_off_card3v3(struct rtsx_chip *chip) return STATUS_FAIL; } - RTSX_WRITE_REG(chip, CARD_OE, XD_OUTPUT_EN, 0); + retval = rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0); + if (retval) { + rtsx_trace(chip); + return retval; + } if (!chip->ft2_fast_mode) { retval = card_power_off(chip, XD_CARD); @@ -2216,7 +2312,11 @@ int xd_power_off_card3v3(struct rtsx_chip *chip) return STATUS_FAIL; } } else { - RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, 0xDF); + retval = rtsx_write_register(chip, FPGA_PULL_CTL, 0xFF, 0xDF); + if (retval) { + rtsx_trace(chip); + return retval; + } } return STATUS_SUCCESS;