From: Guzman Lugo, Fernando Date: Fri, 14 Jan 2011 05:34:52 +0000 (-0600) Subject: staging: tidspbridge: configure full L1 MMU range X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=8e290fd41a15e392af87a33c9c4db3daffcd558b;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git staging: tidspbridge: configure full L1 MMU range IVA MMU can manage up to 4GB of address space through its page tables, given that it's L1 is divided into 1MB sections it requires at least 16KB for its table which represents 4096 entries of 32 bits each. Previously, only 1GB was being handled by setting the page table size to 4KB, any virtual address beyond of the L1 size used, would fall into memory that does not belong to L1 translation tables, leading to unpredictable results. So, set the L1 table size to cover the entire MMU range (4GB) whether is meant to be used or not. Reported-by: Felipe Contreras Signed-off-by: Fernando Guzman Lugo Signed-off-by: Felipe Contreras Signed-off-by: Omar Ramirez Luna Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index a3b0a183d570..c3126e2e23f0 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c @@ -786,10 +786,7 @@ static int bridge_dev_create(struct bridge_dev_context pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL); if (pt_attrs != NULL) { - /* Assuming that we use only DSP's memory map - * until 0x4000:0000 , we would need only 1024 - * L1 enties i.e L1 size = 4K */ - pt_attrs->l1_size = 0x1000; + pt_attrs->l1_size = SZ_16K; /* 4096 entries of 32 bits */ align_size = pt_attrs->l1_size; /* Align sizes are expected to be power of 2 */ /* we like to get aligned on L1 table size */