From: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Date: Mon, 4 Mar 2013 14:26:56 +0000 (+0200)
Subject: mtd: nand: provision full ID support
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=8e12b474f9a2349bcaebda65bdc38e8398ff408e;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

mtd: nand: provision full ID support

Up until now we identified NAND chips by the 'device ID' part of the full chip
ID array, which is the second full ID array byte. However, the newest flashes
use the same device ID for chips with identical page and eraseblock sizes, but
different OOB sizes. And unfortunately, it is not clear if there is a
"standard" way to fetch the OOB size from chip's full ID array. Here is an
example:

Toshiba TC58NVG2S0F: 0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08
Toshiba TC58NVG3S0F: 0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08

The first one is a 512MiB NAND chip with 4KiB NAND pages, 256KiB eraseblock
size and 224 bytes OOB. The second one is a 1GiB NAND chip with the same page
and eraseblock sizes, but with 232 bytes OOB.

This means that we have to store full ID in our NAND flashes table in order to
distinguish between these 2.

This patch adds the 'id[8]' field to the 'struct nand_flash_dev' structure, and
it makes it to be a part of anonymous union, where the second member is a
structure containing the 'mfr_id' and 'dev_id' bytes. The union makes sure that
'mfr_id' refers the same RAM address as 'id[0]' and 'dev_id' refers the same
RAM address as 'id[1]'. The only motivation for the union is an assumption that
'type->dev_id' is more readable than 'type->id[1]'.

Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
---

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 63b319a6f98c..9a1b74c85044 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -551,9 +551,9 @@ struct nand_chip {
  * defined the chip, including the geometry (chip size, eraseblock size, page
  * size).
  */
-#define LEGACY_ID_NAND(nm, devid, pagesz, chipsz, erasesz, opts) \
-	{ .name = (nm), .dev_id = (devid), .pagesize = (pagesz), \
-	  .chipsize = (chipsz), .erasesize = (erasesz),          \
+#define LEGACY_ID_NAND(nm, devid, pagesz, chipsz, erasesz, opts)       \
+	{ .name = (nm), {{ .dev_id = (devid) }}, .pagesize = (pagesz), \
+	  .chipsize = (chipsz), .erasesize = (erasesz),                \
 	  .options = (opts) }
 
 /*
@@ -566,14 +566,19 @@ struct nand_chip {
  * buswidth), and the page size, eraseblock size, and OOB size could vary while
  * using the same device ID.
  */
-#define EXTENDED_ID_NAND(nm, devid, chipsz, opts)                \
-	{ .name = (nm), .dev_id = (devid), .chipsize = (chipsz), \
+#define EXTENDED_ID_NAND(nm, devid, chipsz, opts)                      \
+	{ .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
 	  .options = (opts) }
 
 /**
  * struct nand_flash_dev - NAND Flash Device ID Structure
  * @name: a human-readable name of the NAND chip
  * @dev_id: the device ID (the second byte of the full chip ID array)
+ * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
+ *          memory address as @id[0])
+ * @dev_id: device ID part of the full chip ID array (refers the same memory
+ *          address as @id[1])
+ * @id: full device ID array
  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
  *            well as the eraseblock size) is determined from the extended NAND
  *            chip ID array)
@@ -583,7 +588,13 @@ struct nand_chip {
  */
 struct nand_flash_dev {
 	char *name;
-	int dev_id;
+	union {
+		struct {
+			uint8_t mfr_id;
+			uint8_t dev_id;
+		};
+		uint8_t id[8];
+	};
 	unsigned long pagesize;
 	unsigned long chipsize;
 	unsigned long erasesize;