From: Ben Skeggs Date: Mon, 13 May 2013 04:45:56 +0000 (+1000) Subject: drm/nvc3/gr: update initial register/context values X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=8b637ae3a3d8142db23eed3100245c2a2390358b;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/nvc3/gr: update initial register/context values Signed-off-by: Ben Skeggs --- diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c index 416dc9b16978..27e97c0e45ad 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c @@ -1326,6 +1326,7 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv) switch (nv_device(priv)->chipset) { case 0xc0: + case 0xc3: case 0xd9: case 0xd7: break; @@ -1473,6 +1474,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x40402c, 0x00000000); break; case 0xc0: + case 0xc3: default: break; } @@ -1493,6 +1495,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x4040c8, 0xf0000087); switch (nv_device(priv)->chipset) { case 0xc0: + case 0xc3: case 0xd9: case 0xd7: nv_wr32(priv, 0x4040d0, 0x00000000); @@ -1520,6 +1523,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) case 0xd7: break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x404174, 0x00000000); break; @@ -1662,6 +1666,7 @@ nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x405834, 0x08000000); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x405800, 0x078000bf); nv_wr32(priv, 0x405830, 0x02180000); @@ -1703,6 +1708,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x4064bc, 0x00000000); break; case 0xc0: + case 0xc3: default: break; } @@ -1714,6 +1720,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x4064c4, 0x0086ffff); break; case 0xc0: + case 0xc3: default: break; } @@ -1753,6 +1760,7 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x408804, 0x00000040); switch (nv_device(priv)->chipset) { case 0xc0: + case 0xc3: nv_wr32(priv, 0x408808, 0x0003e00d); nv_wr32(priv, 0x408900, 0x3080b801); nv_wr32(priv, 0x408904, 0x02000001); @@ -1797,6 +1805,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) case 0xd7: break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x418408, 0x00000000); break; @@ -1809,6 +1818,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x418414, 0x02200fff); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x418414, 0x00200fff); break; @@ -1833,6 +1843,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x41870c, 0x00000000); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x41870c, 0x07c80000); break; @@ -1844,6 +1855,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x418800, 0x7006860a); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x418800, 0x0006860a); break; @@ -1859,6 +1871,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x418830, 0x10000001); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x418830, 0x00000001); break; @@ -1879,6 +1892,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x4188fc, 0x20100008); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x4188fc, 0x00100000); break; @@ -1902,6 +1916,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x418b00, 0x00000006); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x418b00, 0x00000000); break; @@ -1929,6 +1944,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x418c6c, 0x00000001); break; case 0xc0: + case 0xc3: default: break; } @@ -1954,6 +1970,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419864, 0x00000129); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x419864, 0x0000012a); break; @@ -1968,6 +1985,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) switch (nv_device(priv)->chipset) { case 0xc0: break; + case 0xc3: default: nv_wr32(priv, 0x419a1c, 0x00000000); nv_wr32(priv, 0x419a20, 0x00000800); @@ -1981,6 +1999,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) case 0xd7: nv_wr32(priv, 0x00419ac4, 0x0017f440); break; + case 0xc3: default: nv_wr32(priv, 0x00419ac4, 0x0007f440); break; @@ -1999,6 +2018,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419be0, 0x00400001); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x419be0, 0x00000001); break; @@ -2010,6 +2030,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419c00, 0x0000000a); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x419c00, 0x00000002); break; @@ -2018,6 +2039,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419c08, 0x00000002); nv_wr32(priv, 0x419c20, 0x00000000); switch (nv_device(priv)->chipset) { + case 0xc3: case 0xce: case 0xcf: nv_wr32(priv, 0x419cb0, 0x00020048); @@ -2042,6 +2064,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419d20, 0x12180000); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x419d20, 0x02180000); break; @@ -2054,6 +2077,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419d44, 0x02180218); break; case 0xc0: + case 0xc3: default: break; } @@ -2090,6 +2114,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) case 0xd7: nv_wr32(priv, 0x419ee0, 0x00010110); break; + case 0xc3: default: nv_wr32(priv, 0x419ee0, 0x00011110); break; @@ -2100,6 +2125,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419f50, 0x00000000); nv_wr32(priv, 0x419f54, 0x00000000); break; + case 0xc3: case 0xd9: case 0xd7: nv_wr32(priv, 0x419f30, 0x00000000); @@ -2436,6 +2462,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) nv_icmd(priv, i, 0x00000040); break; case 0xc0: + case 0xc3: default: break; } @@ -2454,6 +2481,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) nv_icmd(priv, i, 0x0000c080); break; case 0xc0: + case 0xc3: break; default: break; @@ -3282,6 +3310,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) switch (nv_device(priv)->chipset) { case 0xc0: + case 0xc3: nv_mthd(priv, 0x902d, 0x3410, 0x00000000); break; case 0xd9: diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc index 1034ff15b032..f9874a536969 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc @@ -58,10 +58,10 @@ chipsets: .b16 #nvc0_tpc_mmio_head .b16 #nvc1_tpc_mmio_tail .b8 0xc3 0 0 0 -.b16 #nvc0_gpc_mmio_head -.b16 #nvc0_gpc_mmio_tail -.b16 #nvc0_tpc_mmio_head -.b16 #nvc3_tpc_mmio_tail +.b16 #nnvc0_gpc_mmio_head +.b16 #nnvc0_gpc_mmio_tail +.b16 #nnvc3_tpc_mmio_head +.b16 #nnvc3_tpc_mmio_tail .b8 0xc4 0 0 0 .b16 #nvc0_gpc_mmio_head .b16 #nvc0_gpc_mmio_tail @@ -234,6 +234,31 @@ mmctx_data(0x000698, 1) mmctx_data(0x000750, 2) nnvc0_tpc_mmio_tail: +nnvc3_tpc_mmio_head: +mmctx_data(0x000018, 1) +mmctx_data(0x00003c, 1) +mmctx_data(0x000048, 1) +mmctx_data(0x000064, 1) +mmctx_data(0x000088, 1) +mmctx_data(0x000200, 6) +mmctx_data(0x00021c, 2) +mmctx_data(0x0002c4, 1) +mmctx_data(0x000300, 6) +mmctx_data(0x0003d0, 1) +mmctx_data(0x0003e0, 2) +mmctx_data(0x000400, 3) +mmctx_data(0x000420, 1) +mmctx_data(0x0004b0, 1) +mmctx_data(0x0004e8, 1) +mmctx_data(0x0004f4, 1) +mmctx_data(0x000520, 2) +mmctx_data(0x000604, 4) +mmctx_data(0x000644, 20) +mmctx_data(0x000698, 1) +mmctx_data(0x0006e0, 1) +mmctx_data(0x000730, 11) +nnvc3_tpc_mmio_tail: + nvd9_tpc_mmio_head: mmctx_data(0x000018, 1) mmctx_data(0x00003c, 1) diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h index 427ddf06316c..0db048131d30 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h @@ -40,8 +40,8 @@ uint32_t nvc0_grgpc_data[] = { 0x013800d4, 0x02640200, 0x000000c3, - 0x013400d4, - 0x02600200, + 0x01980138, + 0x030802b0, 0x000000c4, 0x013400d4, 0x02600200, @@ -56,10 +56,10 @@ uint32_t nvc0_grgpc_data[] = { 0x025c0200, 0x000000d9, 0x02000198, - 0x030c02b0, + 0x03640308, 0x000000d7, 0x02000198, - 0x030c02b0, + 0x03640308, 0x00000000, /* 0x00d4: nvc0_gpc_mmio_head */ 0x00000380, @@ -194,7 +194,31 @@ uint32_t nvc0_grgpc_data[] = { 0x00000698, 0x04000750, /* 0x02b0: nnvc0_tpc_mmio_tail */ -/* 0x02b0: nvd9_tpc_mmio_head */ +/* 0x02b0: nnvc3_tpc_mmio_head */ + 0x00000018, + 0x0000003c, + 0x00000048, + 0x00000064, + 0x00000088, + 0x14000200, + 0x0400021c, + 0x000002c4, + 0x14000300, + 0x000003d0, + 0x040003e0, + 0x08000400, + 0x00000420, + 0x000004b0, + 0x000004e8, + 0x000004f4, + 0x04000520, + 0x0c000604, + 0x4c000644, + 0x00000698, + 0x000006e0, + 0x28000730, +/* 0x0308: nnvc3_tpc_mmio_tail */ +/* 0x0308: nvd9_tpc_mmio_head */ 0x00000018, 0x0000003c, 0x00000048, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc index 9f0768e2719d..58e8d010ae50 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc @@ -54,8 +54,8 @@ chipsets: .b16 #nvc0_hub_mmio_head .b16 #nvc1_hub_mmio_tail .b8 0xc3 0 0 0 -.b16 #nvc0_hub_mmio_head -.b16 #nvc0_hub_mmio_tail +.b16 #nnvc0_hub_mmio_head +.b16 #nnvc0_hub_mmio_tail .b8 0xc4 0 0 0 .b16 #nvc0_hub_mmio_head .b16 #nvc0_hub_mmio_tail diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h index fc5f9727ae76..6466bcf8db97 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h @@ -207,7 +207,7 @@ uint32_t nvc0_grhub_data[] = { 0x000000c1, 0x03ec034c, 0x000000c3, - 0x03e8034c, + 0x048803ec, 0x000000c4, 0x03e8034c, 0x000000c8, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c index 9d705bab9dcd..5f39dd20842f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c @@ -753,6 +753,7 @@ nvc0_graph_init_unk64xx(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x4064f8, 0x00000000); break; case 0xc0: + case 0xc3: default: break; } @@ -764,6 +765,7 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x405844, 0x00ffffff); nv_wr32(priv, 0x405850, 0x00000000); switch (nv_device(priv)->chipset) { + case 0xc3: case 0xd9: case 0xd7: nv_wr32(priv, 0x405900, 0x00002834); @@ -780,6 +782,7 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x40592c, 0x00000000); break; case 0xc0: + case 0xc3: default: break; } @@ -800,6 +803,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x418408, 0x00000000); break; case 0xc0: + case 0xc3: default: break; } @@ -811,6 +815,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x4184a8, 0x00000000); break; case 0xc0: + case 0xc3: default: break; } @@ -822,6 +827,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x418714, 0x00000000); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x418714, 0x80000000); break; @@ -837,6 +843,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x4188c8, 0x00000000); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x4188c8, 0x80000000); break; @@ -859,6 +866,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x418c68, 0x00000000); break; case 0xc0: + case 0xc3: default: break; } @@ -870,6 +878,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x418cb8, 0x00000000); break; case 0xc0: + case 0xc3: default: break; } @@ -882,6 +891,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x418f00, 0x00000000); break; case 0xc0: + case 0xc3: default: break; } @@ -894,6 +904,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x418e00, 0x00000003); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x418e00, 0x00000050); break; @@ -906,6 +917,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x418e20, 0x00000000); break; case 0xc0: + case 0xc3: default: break; } @@ -921,6 +933,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419d10, 0x00000014); nv_wr32(priv, 0x419ab0, 0x00000000); switch (nv_device(priv)->chipset) { + case 0xc3: case 0xd9: case 0xd7: nv_wr32(priv, 0x419ac8, 0x00000000); @@ -939,6 +952,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x41980c, 0x00000010); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x41980c, 0x00000000); break; @@ -950,6 +964,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419814, 0x00000004); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x419814, 0x00000000); break; @@ -961,6 +976,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x41984c, 0x0000a918); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x41984c, 0x00005bc5); break; @@ -970,6 +986,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419858, 0x00000000); nv_wr32(priv, 0x41985c, 0x00000000); switch (nv_device(priv)->chipset) { + case 0xc3: case 0xd9: case 0xd7: nv_wr32(priv, 0x419880, 0x00000002); @@ -994,6 +1011,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419bfc, 0x00000000); break; case 0xc0: + case 0xc3: default: break; } @@ -1005,6 +1023,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419d4c, 0x00000000); break; case 0xc0: + case 0xc3: default: break; } @@ -1018,6 +1037,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419ea8, 0x02001100); break; case 0xc0: + case 0xc3: default: nv_wr32(priv, 0x419ea8, 0x00001100); break; @@ -1029,6 +1049,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419ebc, 0x00000000); nv_wr32(priv, 0x419ec0, 0x00000000); switch (nv_device(priv)->chipset) { + case 0xc3: case 0xd9: case 0xd7: nv_wr32(priv, 0x419ec8, 0x0e063818); @@ -1311,6 +1332,7 @@ nvc0_graph_init(struct nouveau_object *object) switch (nv_device(priv)->chipset) { case 0xc0: + case 0xc3: case 0xd9: case 0xd7: nvc0_graph_init_unk40xx(priv);