From: Ralf Baechle Date: Tue, 22 Nov 2005 17:53:59 +0000 (+0000) Subject: [MIPS] R10000 and R12000 need to set MIPS_CPU_4K_CACHE ... X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=8b36612a23fda542fab5f0c6c26e15e2178e3d0e;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git [MIPS] R10000 and R12000 need to set MIPS_CPU_4K_CACHE ... ... because they have R4000-style caches. Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index a263fb7a3971..5e1b08b00a33 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -417,7 +417,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) case PRID_IMP_R10000: c->cputype = CPU_R10000; c->isa_level = MIPS_CPU_ISA_IV; - c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | MIPS_CPU_LLSC; @@ -426,7 +426,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) case PRID_IMP_R12000: c->cputype = CPU_R12000; c->isa_level = MIPS_CPU_ISA_IV; - c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | MIPS_CPU_LLSC;