From: Arnaldo Carvalho de Melo Date: Fri, 15 Jul 2016 13:05:19 +0000 (-0300) Subject: perf tools: Just pr_debug() about not being able to read cacheline_size X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=8811e8ea14c1056b09c794c67836b8a84584ddef;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git perf tools: Just pr_debug() about not being able to read cacheline_size So far the cacheline_size is only useful for the "dcacheline" --sort order, i.e. if that is not used, which is the norm, then the user shouldn't care that he is running this, say, on an Android system where sysconf(_SC_LEVEL1_DCACHE_LINESIZE) and the /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size sysfs file isn't available. An upcoming patch will emit an warning only for "--sort ...,dcacheline,...". Cc: Adrian Hunter Cc: Chris Phlipot Cc: David Ahern Cc: Jiri Olsa Cc: Namhyung Kim Cc: Wang Nan Link: http://lkml.kernel.org/n/tip-580cnkvftunyvt9n7unsholi@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- diff --git a/tools/perf/perf.c b/tools/perf/perf.c index 4b2ff021434c..64c06961bfe4 100644 --- a/tools/perf/perf.c +++ b/tools/perf/perf.c @@ -503,7 +503,7 @@ void pthread__unblock_sigwinch(void) static void cache_line_size(int *cacheline_sizep) { if (sysfs__read_int("devices/system/cpu/cpu0/cache/index0/coherency_line_size", cacheline_sizep)) - perror("cannot determine cache line size"); + pr_debug("cannot determine cache line size"); } #endif