From: Ben Skeggs Date: Wed, 14 Jan 2015 05:30:22 +0000 (+1000) Subject: drm/nouveau/msppp: namespace + nvidia gpu names (no binary change) X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=87a876579abd1df8479ad90974492ec0a145d165;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/nouveau/msppp: namespace + nvidia gpu names (no binary change) The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs --- diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h index 5f2f82ed9598..c6c69d0a8d01 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h @@ -1,7 +1,6 @@ -#ifndef __NOUVEAU_MSPPP_H__ -#define __NOUVEAU_MSPPP_H__ - -extern struct nouveau_oclass nv98_msppp_oclass; -extern struct nouveau_oclass nvc0_msppp_oclass; - +#ifndef __NVKM_MSPPP_H__ +#define __NVKM_MSPPP_H__ +#include +extern struct nvkm_oclass g98_msppp_oclass; +extern struct nvkm_oclass gf100_msppp_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 67db4e6ca489..a5a9c8bf8f0d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -96,7 +96,7 @@ gm100_identify(struct nouveau_device *device) #if 0 device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; #endif break; case 0x124: @@ -139,7 +139,7 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; #endif break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 9ea3a60ab417..a7838a7c1901 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -257,7 +257,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; break; @@ -315,7 +315,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; break; @@ -344,7 +344,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv84_pm_oclass; break; @@ -374,7 +374,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; @@ -404,7 +404,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; @@ -434,7 +434,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; @@ -464,7 +464,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nv98_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = >215_ce_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = nva3_pm_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index ff39357a2bf2..83dd982b1c4c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c @@ -86,7 +86,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; @@ -119,7 +119,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; @@ -152,7 +152,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; @@ -184,7 +184,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; @@ -217,7 +217,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; @@ -249,7 +249,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; @@ -281,7 +281,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass; @@ -314,7 +314,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; @@ -344,7 +344,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index 56c3e67b8962..5676a0251c79 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c @@ -90,7 +90,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; break; case 0xe7: @@ -124,7 +124,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; break; case 0xe6: @@ -158,7 +158,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nve0_pm_oclass; break; case 0xea: @@ -214,7 +214,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass; break; case 0xf1: @@ -248,7 +248,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; device->oclass[NVDEV_ENGINE_PM ] = &nvf0_pm_oclass; break; case 0x106: @@ -282,7 +282,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; break; case 0x108: device->cname = "GK208"; @@ -315,7 +315,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass; - device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass; + device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; break; default: nv_fatal(device, "unknown Kepler chipset\n"); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild index 9b90ce948425..4576a9eee39d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild @@ -1,2 +1,2 @@ -nvkm-y += nvkm/engine/msppp/nv98.o -nvkm-y += nvkm/engine/msppp/nvc0.o +nvkm-y += nvkm/engine/msppp/g98.o +nvkm-y += nvkm/engine/msppp/gf100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c new file mode 100644 index 000000000000..7a602a2dec94 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c @@ -0,0 +1,109 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin + */ +#include +#include + +struct g98_msppp_priv { + struct nvkm_falcon base; +}; + +/******************************************************************************* + * MSPPP object classes + ******************************************************************************/ + +static struct nvkm_oclass +g98_msppp_sclass[] = { + { 0x88b3, &nvkm_object_ofuncs }, + { 0x85b3, &nvkm_object_ofuncs }, + {}, +}; + +/******************************************************************************* + * PMSPPP context + ******************************************************************************/ + +static struct nvkm_oclass +g98_msppp_cclass = { + .handle = NV_ENGCTX(MSPPP, 0x98), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, + }, +}; + +/******************************************************************************* + * PMSPPP engine/subdev functions + ******************************************************************************/ + +static int +g98_msppp_init(struct nvkm_object *object) +{ + struct g98_msppp_priv *priv = (void *)object; + int ret; + + ret = nvkm_falcon_init(&priv->base); + if (ret) + return ret; + + nv_wr32(priv, 0x086010, 0x0000ffd2); + nv_wr32(priv, 0x08601c, 0x0000fff2); + return 0; +} + +static int +g98_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct g98_msppp_priv *priv; + int ret; + + ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true, + "PMSPPP", "msppp", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00400002; + nv_engine(priv)->cclass = &g98_msppp_cclass; + nv_engine(priv)->sclass = g98_msppp_sclass; + return 0; +} + +struct nvkm_oclass +g98_msppp_oclass = { + .handle = NV_ENGINE(MSPPP, 0x98), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g98_msppp_ctor, + .dtor = _nvkm_falcon_dtor, + .init = g98_msppp_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c new file mode 100644 index 000000000000..6047baee1f75 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c @@ -0,0 +1,109 @@ +/* + * Copyright 2012 Maarten Lankhorst + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Maarten Lankhorst + */ +#include +#include + +struct gf100_msppp_priv { + struct nvkm_falcon base; +}; + +/******************************************************************************* + * MSPPP object classes + ******************************************************************************/ + +static struct nvkm_oclass +gf100_msppp_sclass[] = { + { 0x90b3, &nvkm_object_ofuncs }, + {}, +}; + +/******************************************************************************* + * PMSPPP context + ******************************************************************************/ + +static struct nvkm_oclass +gf100_msppp_cclass = { + .handle = NV_ENGCTX(MSPPP, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = _nvkm_falcon_context_ctor, + .dtor = _nvkm_falcon_context_dtor, + .init = _nvkm_falcon_context_init, + .fini = _nvkm_falcon_context_fini, + .rd32 = _nvkm_falcon_context_rd32, + .wr32 = _nvkm_falcon_context_wr32, + }, +}; + +/******************************************************************************* + * PMSPPP engine/subdev functions + ******************************************************************************/ + +static int +gf100_msppp_init(struct nvkm_object *object) +{ + struct gf100_msppp_priv *priv = (void *)object; + int ret; + + ret = nvkm_falcon_init(&priv->base); + if (ret) + return ret; + + nv_wr32(priv, 0x086010, 0x0000fff2); + nv_wr32(priv, 0x08601c, 0x0000fff2); + return 0; +} + +static int +gf100_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct gf100_msppp_priv *priv; + int ret; + + ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true, + "PMSPPP", "msppp", &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + nv_subdev(priv)->unit = 0x00000002; + nv_subdev(priv)->intr = nvkm_falcon_intr; + nv_engine(priv)->cclass = &gf100_msppp_cclass; + nv_engine(priv)->sclass = gf100_msppp_sclass; + return 0; +} + +struct nvkm_oclass +gf100_msppp_oclass = { + .handle = NV_ENGINE(MSPPP, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_msppp_ctor, + .dtor = _nvkm_falcon_dtor, + .init = gf100_msppp_init, + .fini = _nvkm_falcon_fini, + .rd32 = _nvkm_falcon_rd32, + .wr32 = _nvkm_falcon_wr32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c deleted file mode 100644 index c044943c3fc7..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin - */ - -#include -#include - -struct nv98_msppp_priv { - struct nouveau_falcon base; -}; - -/******************************************************************************* - * MSPPP object classes - ******************************************************************************/ - -static struct nouveau_oclass -nv98_msppp_sclass[] = { - { 0x88b3, &nouveau_object_ofuncs }, - { 0x85b3, &nouveau_object_ofuncs }, - {}, -}; - -/******************************************************************************* - * PMSPPP context - ******************************************************************************/ - -static struct nouveau_oclass -nv98_msppp_cclass = { - .handle = NV_ENGCTX(MSPPP, 0x98), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, - }, -}; - -/******************************************************************************* - * PMSPPP engine/subdev functions - ******************************************************************************/ - -static int -nv98_msppp_init(struct nouveau_object *object) -{ - struct nv98_msppp_priv *priv = (void *)object; - int ret; - - ret = nouveau_falcon_init(&priv->base); - if (ret) - return ret; - - nv_wr32(priv, 0x086010, 0x0000ffd2); - nv_wr32(priv, 0x08601c, 0x0000fff2); - return 0; -} - -static int -nv98_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nv98_msppp_priv *priv; - int ret; - - ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true, - "PMSPPP", "msppp", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00400002; - nv_engine(priv)->cclass = &nv98_msppp_cclass; - nv_engine(priv)->sclass = nv98_msppp_sclass; - return 0; -} - -struct nouveau_oclass -nv98_msppp_oclass = { - .handle = NV_ENGINE(MSPPP, 0x98), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv98_msppp_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nv98_msppp_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c deleted file mode 100644 index 91398e639395..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright 2012 Maarten Lankhorst - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Maarten Lankhorst - */ - -#include -#include - -struct nvc0_msppp_priv { - struct nouveau_falcon base; -}; - -/******************************************************************************* - * MSPPP object classes - ******************************************************************************/ - -static struct nouveau_oclass -nvc0_msppp_sclass[] = { - { 0x90b3, &nouveau_object_ofuncs }, - {}, -}; - -/******************************************************************************* - * PMSPPP context - ******************************************************************************/ - -static struct nouveau_oclass -nvc0_msppp_cclass = { - .handle = NV_ENGCTX(MSPPP, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = _nouveau_falcon_context_ctor, - .dtor = _nouveau_falcon_context_dtor, - .init = _nouveau_falcon_context_init, - .fini = _nouveau_falcon_context_fini, - .rd32 = _nouveau_falcon_context_rd32, - .wr32 = _nouveau_falcon_context_wr32, - }, -}; - -/******************************************************************************* - * PMSPPP engine/subdev functions - ******************************************************************************/ - -static int -nvc0_msppp_init(struct nouveau_object *object) -{ - struct nvc0_msppp_priv *priv = (void *)object; - int ret; - - ret = nouveau_falcon_init(&priv->base); - if (ret) - return ret; - - nv_wr32(priv, 0x086010, 0x0000fff2); - nv_wr32(priv, 0x08601c, 0x0000fff2); - return 0; -} - -static int -nvc0_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nvc0_msppp_priv *priv; - int ret; - - ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true, - "PMSPPP", "msppp", &priv); - *pobject = nv_object(priv); - if (ret) - return ret; - - nv_subdev(priv)->unit = 0x00000002; - nv_subdev(priv)->intr = nouveau_falcon_intr; - nv_engine(priv)->cclass = &nvc0_msppp_cclass; - nv_engine(priv)->sclass = nvc0_msppp_sclass; - return 0; -} - -struct nouveau_oclass -nvc0_msppp_oclass = { - .handle = NV_ENGINE(MSPPP, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_msppp_ctor, - .dtor = _nouveau_falcon_dtor, - .init = nvc0_msppp_init, - .fini = _nouveau_falcon_fini, - .rd32 = _nouveau_falcon_rd32, - .wr32 = _nouveau_falcon_wr32, - }, -};