From: David S. Miller Date: Sat, 27 Jan 2007 02:48:16 +0000 (-0800) Subject: [SPARC64]: Set g4/g5 properly in sun4v dtlb-prot handling. X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=86d43258bcad2068744c85181b97bb35ab27a74d;p=GitHub%2Fmt8127%2Fandroid_kernel_alcatel_ttab.git [SPARC64]: Set g4/g5 properly in sun4v dtlb-prot handling. Mirror the logic in the sun4u handler, we have to update both registers even when we branch out to window fault fixup handling. The way it works is that if we are in etrap processing a fault already, g4/g5 holds the original fault information. If we take a window spill fault while doing etrap, then we put the window spill fault info into g4/g5 and this is what the top-level fault handler ends up processing first. Then we retry the originally faulting instruction, and process the original fault at that time. This is all necessary because of how constrained the trap registers are in these code paths. These cases trigger very rarely, so even if there is some performance implication it's doesn't happen very often. In fact the rarity is why it took so long to trigger and find this particular bug. Signed-off-by: David S. Miller --- diff --git a/arch/sparc64/kernel/sun4v_tlb_miss.S b/arch/sparc64/kernel/sun4v_tlb_miss.S index b731881224e8..9871dbb1ab42 100644 --- a/arch/sparc64/kernel/sun4v_tlb_miss.S +++ b/arch/sparc64/kernel/sun4v_tlb_miss.S @@ -142,9 +142,9 @@ sun4v_dtlb_prot: rdpr %tl, %g1 cmp %g1, 1 bgu,pn %xcc, winfix_trampoline - nop - ba,pt %xcc, sparc64_realfault_common mov FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4 + ba,pt %xcc, sparc64_realfault_common + nop /* Called from trap table: * %g4: vaddr