From: Keith Packard <keithp@keithp.com>
Date: Thu, 20 Oct 2011 20:40:33 +0000 (-0700)
Subject: Merge branch 'edp-training-fixes' into drm-intel-next
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=86a3073e480c522f12e5291a462f68f6ee30aee3;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

Merge branch 'edp-training-fixes' into drm-intel-next

Conflicts:
	drivers/gpu/drm/i915/intel_dp.c

Just whitespace change conflicts
---

86a3073e480c522f12e5291a462f68f6ee30aee3
diff --cc drivers/gpu/drm/i915/intel_dp.c
index 6cbde9ff1ec6,6db2a2d824c0..3d73374c20d1
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -843,7 -985,7 +989,7 @@@ static void ironlake_edp_panel_vdd_off(
  }
  
  /* Returns true if the panel was already on when called */
- static bool ironlake_edp_panel_on(struct intel_dp *intel_dp)
 -static void ironlake_edp_panel_on (struct intel_dp *intel_dp)
++static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
  {
  	struct drm_device *dev = intel_dp->base.base.dev;
  	struct drm_i915_private *dev_priv = dev->dev_private;
@@@ -881,28 -1032,43 +1036,43 @@@ static void ironlake_edp_panel_off(stru
  	u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
  		PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
  
+ 	if (!is_edp(intel_dp))
+ 		return;
  	pp = I915_READ(PCH_PP_CONTROL);
+ 	pp &= ~PANEL_UNLOCK_MASK;
+ 	pp |= PANEL_UNLOCK_REGS;
+ 
+ 	if (IS_GEN5(dev)) {
+ 		/* ILK workaround: disable reset around power sequence */
+ 		pp &= ~PANEL_POWER_RESET;
+ 		I915_WRITE(PCH_PP_CONTROL, pp);
+ 		POSTING_READ(PCH_PP_CONTROL);
+ 	}
  
- 	/* ILK workaround: disable reset around power sequence */
- 	pp &= ~PANEL_POWER_RESET;
- 	I915_WRITE(PCH_PP_CONTROL, pp);
- 	POSTING_READ(PCH_PP_CONTROL);
+ 	intel_dp->panel_off_jiffies = jiffies;
  
- 	pp &= ~POWER_TARGET_ON;
- 	I915_WRITE(PCH_PP_CONTROL, pp);
- 	POSTING_READ(PCH_PP_CONTROL);
+ 	if (IS_GEN5(dev)) {
+ 		pp &= ~POWER_TARGET_ON;
+ 		I915_WRITE(PCH_PP_CONTROL, pp);
+ 		POSTING_READ(PCH_PP_CONTROL);
+ 		pp &= ~POWER_TARGET_ON;
+ 		I915_WRITE(PCH_PP_CONTROL, pp);
+ 		POSTING_READ(PCH_PP_CONTROL);
+ 		msleep(intel_dp->panel_power_cycle_delay);
  
- 	if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
- 		DRM_ERROR("panel off wait timed out: 0x%08x\n",
- 			  I915_READ(PCH_PP_STATUS));
+ 		if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
+ 			DRM_ERROR("panel off wait timed out: 0x%08x\n",
+ 				  I915_READ(PCH_PP_STATUS));
  
- 	pp |= PANEL_POWER_RESET; /* restore panel reset bit */
- 	I915_WRITE(PCH_PP_CONTROL, pp);
- 	POSTING_READ(PCH_PP_CONTROL);
+ 		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
+ 		I915_WRITE(PCH_PP_CONTROL, pp);
+ 		POSTING_READ(PCH_PP_CONTROL);
+ 	}
  }
  
- static void ironlake_edp_backlight_on(struct drm_device *dev)
 -static void ironlake_edp_backlight_on (struct intel_dp *intel_dp)
++static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
  {
+ 	struct drm_device *dev = intel_dp->base.base.dev;
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	u32 pp;
  
@@@ -913,14 -1082,18 +1086,18 @@@
  	 * link.  So delay a bit to make sure the image is solid before
  	 * allowing it to appear.
  	 */
- 	msleep(300);
+ 	msleep(intel_dp->backlight_on_delay);
  	pp = I915_READ(PCH_PP_CONTROL);
+ 	pp &= ~PANEL_UNLOCK_MASK;
+ 	pp |= PANEL_UNLOCK_REGS;
  	pp |= EDP_BLC_ENABLE;
  	I915_WRITE(PCH_PP_CONTROL, pp);
+ 	POSTING_READ(PCH_PP_CONTROL);
  }
  
- static void ironlake_edp_backlight_off(struct drm_device *dev)
 -static void ironlake_edp_backlight_off (struct intel_dp *intel_dp)
++static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
  {
+ 	struct drm_device *dev = intel_dp->base.base.dev;
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	u32 pp;