From: Sujith Manoharan <c_manoha@qualcomm.com>
Date: Mon, 10 Sep 2012 03:50:29 +0000 (+0530)
Subject: ath9k_hw: Program correct PLL value for AR9565
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=8565f8bf478e28a416e2816d906a84e323e5629c;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

ath9k_hw: Program correct PLL value for AR9565

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
---

diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 063d724bba12..47de1a92bfe4 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -918,7 +918,8 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
 	}
 
 	pll = ath9k_hw_compute_pll_control(ah, chan);
-
+	if (AR_SREV_9565(ah))
+		pll |= 0x40000;
 	REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 
 	if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||