From: Catalin Marinas Date: Thu, 30 Apr 2009 16:06:15 +0000 (+0100) Subject: [ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=855c551f5b8cc3815d58e1056c1f1e7c461e2d24;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git [ARM] 5490/1: ARM errata: Processor deadlock when a false hazard is created This patch adds a workaround for the 458693 Cortex-A8 (r2p0) erratum. It sets the corresponding bits in the auxiliary control register so that the PLD instruction becomes a NOP. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 84e4816362b3..49f85664083d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -765,6 +765,19 @@ config ARM_ERRATA_430973 Note that setting specific bits in the ACTLR register may not be available in non-secure mode. +config ARM_ERRATA_458693 + bool "ARM errata: Processor deadlock when a false hazard is created" + depends on CPU_V7 + help + This option enables the workaround for the 458693 Cortex-A8 (r2p0) + erratum. For very specific sequences of memory operations, it is + possible for a hazard condition intended for a cache line to instead + be incorrectly associated with a different cache line. This false + hazard might then cause a processor deadlock. The workaround enables + the L1 caching of the NEON accesses and disables the PLD instruction + in the ACTLR register. Note that setting specific bits in the ACTLR + register may not be available in non-secure mode. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index fc81159596fe..370baa7a0f08 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -187,6 +187,12 @@ __v7_setup: mrc p15, 0, r10, c1, c0, 1 @ read aux control register orr r10, r10, #(1 << 6) @ set IBE to 1 mcr p15, 0, r10, c1, c0, 1 @ write aux control register +#endif +#ifdef CONFIG_ARM_ERRATA_458693 + mrc p15, 0, r10, c1, c0, 1 @ read aux control register + orr r10, r10, #(1 << 5) @ set L1NEON to 1 + orr r10, r10, #(1 << 9) @ set PLDNOP to 1 + mcr p15, 0, r10, c1, c0, 1 @ write aux control register #endif mov r10, #0 #ifdef HARVARD_CACHE