From: Paulo Zanoni Date: Thu, 19 Dec 2013 21:12:29 +0000 (-0200) Subject: drm/i915: add wait_for_vblank argument to intel_enable_pipe X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=851855d8573fc0b9f30901980001d6374d92653e;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git drm/i915: add wait_for_vblank argument to intel_enable_pipe Depending on the HW gen and the connector type, the pipe won't start running right after we call intel_enable_pipe, so that intel_wait_for_vblank call we currently have will just sit there for the full 50ms timeout. So this patch adds an argument that will allow us to avoid the vblank wait in case we want. Currently all the callers still request for the vblank wait, so the behavior should still be the same. We also added a POSTING_READ on the register: previously intel_wait_for_vblank was acting as a POSTING_READ, but now if wait_for_vblank is false we'll stkip it, so we need an explicit POSTING_READ. Signed-off-by: Paulo Zanoni Reviewed-by: Jesse Barnes Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index af98ddb2cde7..c456768282da 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1759,7 +1759,7 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) * returning. */ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, - bool pch_port, bool dsi) + bool pch_port, bool dsi, bool wait_for_vblank) { enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, pipe); @@ -1802,7 +1802,9 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, return; I915_WRITE(reg, val | PIPECONF_ENABLE); - intel_wait_for_vblank(dev_priv->dev, pipe); + POSTING_READ(reg); + if (wait_for_vblank) + intel_wait_for_vblank(dev_priv->dev, pipe); } /** @@ -3599,7 +3601,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) intel_update_watermarks(crtc); intel_enable_pipe(dev_priv, pipe, - intel_crtc->config.has_pch_encoder, false); + intel_crtc->config.has_pch_encoder, false, true); intel_enable_primary_plane(dev_priv, plane, pipe); intel_enable_planes(crtc); intel_crtc_update_cursor(crtc, true); @@ -3745,7 +3747,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_update_watermarks(crtc); intel_enable_pipe(dev_priv, pipe, - intel_crtc->config.has_pch_encoder, false); + intel_crtc->config.has_pch_encoder, false, true); if (intel_crtc->config.has_pch_encoder) lpt_pch_enable(crtc); @@ -4180,7 +4182,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) intel_crtc_load_lut(crtc); intel_update_watermarks(crtc); - intel_enable_pipe(dev_priv, pipe, false, is_dsi); + intel_enable_pipe(dev_priv, pipe, false, is_dsi, true); intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); intel_enable_primary_plane(dev_priv, plane, pipe); intel_enable_planes(crtc); @@ -4219,7 +4221,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) intel_crtc_load_lut(crtc); intel_update_watermarks(crtc); - intel_enable_pipe(dev_priv, pipe, false, false); + intel_enable_pipe(dev_priv, pipe, false, false, true); intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); intel_enable_primary_plane(dev_priv, plane, pipe); intel_enable_planes(crtc);