From: David Howells Date: Fri, 28 May 2010 09:41:16 +0000 (+0100) Subject: FRV: ARCH_KMALLOC_MINALIGN was already defined X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=8507bb0062bff1431bbcce921efe5cd1186fcff2;p=GitHub%2Fmt8127%2Fandroid_kernel_alcatel_ttab.git FRV: ARCH_KMALLOC_MINALIGN was already defined ARCH_KMALLOC_MINALIGN was already defined in asm/mem-layout.h and so shouldn't have been added to asm/cache.h as well, but rather altered in place. The commit that added it to asm/cache.h was: commit 69dcf3db03626c4f18de624e8632454ea12ff260 Author: FUJITA Tomonori Date: Mon May 24 14:32:54 2010 -0700 frv: set ARCH_KMALLOC_MINALIGN Architectures that handle DMA-non-coherent memory need to set ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is DMA-safe: the buffer doesn't share a cache with the others. Signed-off-by: David Howells cc: FUJITA Tomonori Signed-off-by: Linus Torvalds --- diff --git a/arch/frv/include/asm/cache.h b/arch/frv/include/asm/cache.h index 7dc0f0f85b7c..2797163b8f4f 100644 --- a/arch/frv/include/asm/cache.h +++ b/arch/frv/include/asm/cache.h @@ -17,8 +17,6 @@ #define L1_CACHE_SHIFT (CONFIG_FRV_L1_CACHE_SHIFT) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES - #define __cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES))) #define ____cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES))) diff --git a/arch/frv/include/asm/mem-layout.h b/arch/frv/include/asm/mem-layout.h index 2947764fc0e0..ccae981876fa 100644 --- a/arch/frv/include/asm/mem-layout.h +++ b/arch/frv/include/asm/mem-layout.h @@ -35,8 +35,8 @@ * the slab must be aligned such that load- and store-double instructions don't * fault if used */ -#define ARCH_KMALLOC_MINALIGN 8 -#define ARCH_SLAB_MINALIGN 8 +#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES +#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES /*****************************************************************************/ /*