From: Paul Mackerras Date: Wed, 3 Oct 2007 04:41:15 +0000 (+1000) Subject: [POWERPC] Use cache-inhibited large page bit from firmware X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=84fdde5af1eca5ff170d1dff7e2681b0a50a9ecb;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git [POWERPC] Use cache-inhibited large page bit from firmware Discussions with firmware architects have confirmed that the bit in the ibm,pa-features property that indicates support for cache-inhibited large (>= 64kB) page mappings does in fact mean that the hypervisor allows 64kB mappings to I/O devices. Thus we can now enable the code that tests that bit and sets our CPU_FTR_CI_LARGE_PAGE feature bit. Signed-off-by: Paul Mackerras --- diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 172dcc3849a0..9f329a8928ea 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -531,10 +531,7 @@ static struct ibm_pa_feature { {CPU_FTR_CTRL, 0, 0, 3, 0}, {CPU_FTR_NOEXECUTE, 0, 0, 6, 0}, {CPU_FTR_NODSISRALIGN, 0, 1, 1, 1}, -#if 0 - /* put this back once we know how to test if firmware does 64k IO */ {CPU_FTR_CI_LARGE_PAGE, 0, 1, 2, 0}, -#endif {CPU_FTR_REAL_LE, PPC_FEATURE_TRUE_LE, 5, 0, 0}, };