From: Damien Lespiau Date: Fri, 30 Oct 2015 15:53:32 +0000 (+0200) Subject: drm/i915/skl: Expose DC5/DC6 entry counts X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=8337206d3bf088c9f60ada7a71188b7f4b4ec2eb;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git drm/i915/skl: Expose DC5/DC6 entry counts The CSR firmware expose two counters, handy to check if we are indeed entering DC5/DC6. v2: Rebase v3: Take RPM ref before reading (Imre) Signed-off-by: Damien Lespiau Reviewed-by: Rodrigo Vivi (v1) Signed-off-by: Mika Kuoppala Reviewed-by: Imre Deak Link: http://patchwork.freedesktop.org/patch/msgid/1446220412-32574-1-git-send-email-mika.kuoppala@intel.com Tested-by: Daniel Stone # SKL Signed-off-by: Ville Syrjälä --- diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 847753dd47ab..bf04f5bda324 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2811,6 +2811,17 @@ static int i915_dmc_info(struct seq_file *m, void *unused) seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), CSR_VERSION_MINOR(csr->version)); + intel_runtime_pm_get(dev_priv); + + if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) { + seq_printf(m, "DC3 -> DC5 count: %d\n", + I915_READ(SKL_CSR_DC3_DC5_COUNT)); + seq_printf(m, "DC5 -> DC6 count: %d\n", + I915_READ(SKL_CSR_DC5_DC6_COUNT)); + } + + intel_runtime_pm_put(dev_priv); + return 0; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e8f1d4206326..bbfc9d9a5b49 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5697,6 +5697,10 @@ enum skl_disp_power_wells { #define GAMMA_MODE_MODE_12BIT (2 << 0) #define GAMMA_MODE_MODE_SPLIT (3 << 0) +/* DMC/CSR */ +#define SKL_CSR_DC3_DC5_COUNT 0x80030 +#define SKL_CSR_DC5_DC6_COUNT 0x8002C + /* interrupts */ #define DE_MASTER_IRQ_CONTROL (1 << 31) #define DE_SPRITEB_FLIP_DONE (1 << 29)