From: Linus Torvalds Date: Wed, 12 Dec 2012 19:45:16 +0000 (-0800) Subject: Merge tag 'headers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc X-Git-Tag: MMI-PSA29.97-13-9~15407 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=8287361abca36504da813638310d2547469283eb;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git Merge tag 'headers' of git://git./linux/kernel/git/arm/arm-soc Pull ARM SoC Header cleanups from Olof Johansson: "This is a collection of header file cleanups, mostly for OMAP and AT91, that keeps moving the platforms in the direction of multiplatform by removing the need for mach-dependent header files used in drivers and other places." Fix up mostly trivial conflicts as per Olof. * tag 'headers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (106 commits) ARM: OMAP2+: Move iommu/iovmm headers to platform_data ARM: OMAP2+: Make some definitions local ARM: OMAP2+: Move iommu2 to drivers/iommu/omap-iommu2.c ARM: OMAP2+: Move plat/iovmm.h to include/linux/omap-iommu.h ARM: OMAP2+: Move iopgtable header to drivers/iommu/ ARM: OMAP: Merge iommu2.h into iommu.h atmel: move ATMEL_MAX_UART to platform_data/atmel.h ARM: OMAP: Remove omap_init_consistent_dma_size() arm: at91: move at91rm9200 rtc header in drivers/rtc arm: at91: move reset controller header to arm/arm/mach-at91 arm: at91: move pit define to the driver arm: at91: move at91_shdwc.h to arch/arm/mach-at91 arm: at91: move board header to arch/arm/mach-at91 arn: at91: move at91_tc.h to arch/arm/mach-at91 arm: at91 move at91_aic.h to arch/arm/mach-at91 arm: at91 move board.h to arch/arm/mach-at91 arm: at91: move platfarm_data to include/linux/platform_data/atmel.h arm: at91: drop machine defconfig ARM: OMAP: Remove NEED_MACH_GPIO_H ARM: OMAP: Remove unnecessary mach and plat includes ... --- 8287361abca36504da813638310d2547469283eb diff --cc arch/arm/mach-at91/board.h index 000000000000,662451d85fc9..4a234fb2ab3b mode 000000,100644..100644 --- a/arch/arm/mach-at91/board.h +++ b/arch/arm/mach-at91/board.h @@@ -1,0 -1,141 +1,131 @@@ + /* + * arch/arm/mach-at91/include/mach/board.h + * + * Copyright (C) 2005 HP Labs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + /* + * These are data structures found in platform_device.dev.platform_data, + * and describing board-specific data needed by drivers. For example, + * which pin is used for a given GPIO role. + * + * In 2.6, drivers should strongly avoid board-specific knowledge so + * that supporting new boards normally won't require driver patches. + * Most board-specific knowledge should be in arch/.../board-*.c files. + */ + + #ifndef __ASM_ARCH_BOARD_H + #define __ASM_ARCH_BOARD_H + + #include + + /* USB Device */ + extern void __init at91_add_device_udc(struct at91_udc_data *data); + + /* USB High Speed Device */ + extern void __init at91_add_device_usba(struct usba_platform_data *data); + + /* Compact Flash */ + extern void __init at91_add_device_cf(struct at91_cf_data *data); + + /* MMC / SD */ - /* at91_mci platform config */ -struct at91_mmc_data { - int det_pin; /* card detect IRQ */ - unsigned slot_b:1; /* uses Slot B */ - unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ - int wp_pin; /* (SD) writeprotect detect */ - int vcc_pin; /* power switching (high == on) */ -}; -extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data); - + /* atmel-mci platform config */ + extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data); + + extern void __init at91_add_device_eth(struct macb_platform_data *data); + + /* USB Host */ + extern void __init at91_add_device_usbh(struct at91_usbh_data *data); + extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data); + extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data); + + extern void __init at91_add_device_nand(struct atmel_nand_data *data); + + /* I2C*/ + #if defined(CONFIG_ARCH_AT91SAM9G45) + extern void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices); + #else + extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices); + #endif + + /* SPI */ + extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices); + + /* Serial */ + #define ATMEL_UART_CTS 0x01 + #define ATMEL_UART_RTS 0x02 + #define ATMEL_UART_DSR 0x04 + #define ATMEL_UART_DTR 0x08 + #define ATMEL_UART_DCD 0x10 + #define ATMEL_UART_RI 0x20 + + extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins); + + extern struct platform_device *atmel_default_console_device; + + extern void __init at91_add_device_serial(void); + + /* + * PWM + */ + #define AT91_PWM0 0 + #define AT91_PWM1 1 + #define AT91_PWM2 2 + #define AT91_PWM3 3 + + extern void __init at91_add_device_pwm(u32 mask); + + /* + * SSC -- accessed through ssc_request(id). Drivers don't bind to SSC + * platform devices. Their SSC ID is part of their configuration data, + * along with information about which SSC signals they should use. + */ + #define ATMEL_SSC_TK 0x01 + #define ATMEL_SSC_TF 0x02 + #define ATMEL_SSC_TD 0x04 + #define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD) + + #define ATMEL_SSC_RK 0x10 + #define ATMEL_SSC_RF 0x20 + #define ATMEL_SSC_RD 0x40 + #define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD) + + extern void __init at91_add_device_ssc(unsigned id, unsigned pins); + + /* LCD Controller */ + struct atmel_lcdfb_info; + extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data); + + /* AC97 */ + extern void __init at91_add_device_ac97(struct ac97c_platform_data *data); + + /* ISI */ + struct isi_platform_data; + extern void __init at91_add_device_isi(struct isi_platform_data *data, + bool use_pck_as_mck); + + /* Touchscreen Controller */ + extern void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data); + + /* CAN */ + extern void __init at91_add_device_can(struct at91_can_data *data); + + /* LEDs */ + extern void __init at91_gpio_leds(struct gpio_led *leds, int nr); + extern void __init at91_pwm_leds(struct gpio_led *leds, int nr); + + #endif diff --cc arch/arm/mach-omap2/drm.c index 49a7ffb716a5,6282cc826613..fce5aa3fff49 --- a/arch/arm/mach-omap2/drm.c +++ b/arch/arm/mach-omap2/drm.c @@@ -23,11 -23,9 +23,11 @@@ #include #include #include +#include - #include - #include + #include "omap_device.h" + #include "omap_hwmod.h" +#include #if defined(CONFIG_DRM_OMAP) || (CONFIG_DRM_OMAP_MODULE) diff --cc arch/arm/mach-omap2/omap4-common.c index 6f94b4e7b18d,3cfcd41bf8fa..eda316abbff5 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@@ -25,18 -24,15 +25,16 @@@ #include #include #include +#include - #include - #include - #include - #include "omap-wakeupgen.h" - #include "soc.h" #include "common.h" + #include "mmc.h" #include "hsmmc.h" #include "omap4-sar-layout.h" + #include "omap-secure.h" + #include "sram.h" #ifdef CONFIG_CACHE_L2X0 static void __iomem *l2cache_base; diff --cc arch/arm/mach-omap2/omap_hwmod.h index 000000000000,87b59b45c678..87a3c5b7aa74 mode 000000,100644..100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@@ -1,0 -1,675 +1,681 @@@ + /* + * omap_hwmod macros, structures + * + * Copyright (C) 2009-2011 Nokia Corporation + * Copyright (C) 2012 Texas Instruments, Inc. + * Paul Walmsley + * + * Created in collaboration with (alphabetical order): Benoît Cousson, + * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari + * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * These headers and macros are used to define OMAP on-chip module + * data and their integration with other OMAP modules and Linux. + * Copious documentation and references can also be found in the + * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this + * writing). + * + * To do: + * - add interconnect error log structures + * - add pinmuxing + * - init_conn_id_bit (CONNID_BIT_VECTOR) + * - implement default hwmod SMS/SDRC flags? + * - move Linux-specific data ("non-ROM data") out + * + */ + #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H + #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H + + #include + #include + #include + #include + #include + + struct omap_device; + + extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1; + extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; + extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3; + + /* + * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant + * with the original PRCM protocol defined for OMAP2420 + */ + #define SYSC_TYPE1_MIDLEMODE_SHIFT 12 + #define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_TYPE1_MIDLEMODE_SHIFT) + #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8 + #define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_TYPE1_CLOCKACTIVITY_SHIFT) + #define SYSC_TYPE1_SIDLEMODE_SHIFT 3 + #define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_TYPE1_SIDLEMODE_SHIFT) + #define SYSC_TYPE1_ENAWAKEUP_SHIFT 2 + #define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_TYPE1_ENAWAKEUP_SHIFT) + #define SYSC_TYPE1_SOFTRESET_SHIFT 1 + #define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_TYPE1_SOFTRESET_SHIFT) + #define SYSC_TYPE1_AUTOIDLE_SHIFT 0 + #define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_TYPE1_AUTOIDLE_SHIFT) + + /* + * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant + * with the new PRCM protocol defined for new OMAP4 IPs. + */ + #define SYSC_TYPE2_SOFTRESET_SHIFT 0 + #define SYSC_TYPE2_SOFTRESET_MASK (1 << SYSC_TYPE2_SOFTRESET_SHIFT) + #define SYSC_TYPE2_SIDLEMODE_SHIFT 2 + #define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT) + #define SYSC_TYPE2_MIDLEMODE_SHIFT 4 + #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT) + #define SYSC_TYPE2_DMADISABLE_SHIFT 16 + #define SYSC_TYPE2_DMADISABLE_MASK (0x1 << SYSC_TYPE2_DMADISABLE_SHIFT) + + /* + * OCP SYSCONFIG bit shifts/masks TYPE3. + * This is applicable for some IPs present in AM33XX + */ + #define SYSC_TYPE3_SIDLEMODE_SHIFT 0 + #define SYSC_TYPE3_SIDLEMODE_MASK (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT) + #define SYSC_TYPE3_MIDLEMODE_SHIFT 2 + #define SYSC_TYPE3_MIDLEMODE_MASK (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT) + + /* OCP SYSSTATUS bit shifts/masks */ + #define SYSS_RESETDONE_SHIFT 0 + #define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT) + + /* Master standby/slave idle mode flags */ + #define HWMOD_IDLEMODE_FORCE (1 << 0) + #define HWMOD_IDLEMODE_NO (1 << 1) + #define HWMOD_IDLEMODE_SMART (1 << 2) + #define HWMOD_IDLEMODE_SMART_WKUP (1 << 3) + + /* modulemode control type (SW or HW) */ + #define MODULEMODE_HWCTRL 1 + #define MODULEMODE_SWCTRL 2 + + + /** + * struct omap_hwmod_mux_info - hwmod specific mux configuration + * @pads: array of omap_device_pad entries + * @nr_pads: number of omap_device_pad entries + * + * Note that this is currently built during init as needed. + */ + struct omap_hwmod_mux_info { + int nr_pads; + struct omap_device_pad *pads; + int nr_pads_dynamic; + struct omap_device_pad **pads_dynamic; + int *irqs; + bool enabled; + }; + + /** + * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod + * @name: name of the IRQ channel (module local name) + * @irq: IRQ channel ID (should be non-negative except -1 = terminator) + * + * @name should be something short, e.g., "tx" or "rx". It is for use + * by platform_get_resource_byname(). It is defined locally to the + * hwmod. + */ + struct omap_hwmod_irq_info { + const char *name; + s16 irq; + }; + + /** + * struct omap_hwmod_dma_info - DMA channels used by the hwmod + * @name: name of the DMA channel (module local name) + * @dma_req: DMA request ID (should be non-negative except -1 = terminator) + * + * @name should be something short, e.g., "tx" or "rx". It is for use + * by platform_get_resource_byname(). It is defined locally to the + * hwmod. + */ + struct omap_hwmod_dma_info { + const char *name; + s16 dma_req; + }; + + /** + * struct omap_hwmod_rst_info - IPs reset lines use by hwmod + * @name: name of the reset line (module local name) + * @rst_shift: Offset of the reset bit + * @st_shift: Offset of the reset status bit (OMAP2/3 only) + * + * @name should be something short, e.g., "cpu0" or "rst". It is defined + * locally to the hwmod. + */ + struct omap_hwmod_rst_info { + const char *name; + u8 rst_shift; + u8 st_shift; + }; + + /** + * struct omap_hwmod_opt_clk - optional clocks used by this hwmod + * @role: "sys", "32k", "tv", etc -- for use in clk_get() + * @clk: opt clock: OMAP clock name + * @_clk: pointer to the struct clk (filled in at runtime) + * + * The module's interface clock and main functional clock should not + * be added as optional clocks. + */ + struct omap_hwmod_opt_clk { + const char *role; + const char *clk; + struct clk *_clk; + }; + + + /* omap_hwmod_omap2_firewall.flags bits */ + #define OMAP_FIREWALL_L3 (1 << 0) + #define OMAP_FIREWALL_L4 (1 << 1) + + /** + * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data + * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_* + * @l4_fw_region: L4 firewall region ID + * @l4_prot_group: L4 protection group ID + * @flags: (see omap_hwmod_omap2_firewall.flags macros above) + */ + struct omap_hwmod_omap2_firewall { + u8 l3_perm_bit; + u8 l4_fw_region; + u8 l4_prot_group; + u8 flags; + }; + + + /* + * omap_hwmod_addr_space.flags bits + * + * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init. + * ADDR_TYPE_RT: Address space contains module register target data. + */ + #define ADDR_MAP_ON_INIT (1 << 0) /* XXX does not belong */ + #define ADDR_TYPE_RT (1 << 1) + + /** + * struct omap_hwmod_addr_space - address space handled by the hwmod + * @name: name of the address space + * @pa_start: starting physical address + * @pa_end: ending physical address + * @flags: (see omap_hwmod_addr_space.flags macros above) + * + * Address space doesn't necessarily follow physical interconnect + * structure. GPMC is one example. + */ + struct omap_hwmod_addr_space { + const char *name; + u32 pa_start; + u32 pa_end; + u8 flags; + }; + + + /* + * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this + * interface to interact with the hwmod. Used to add sleep dependencies + * when the module is enabled or disabled. + */ + #define OCP_USER_MPU (1 << 0) + #define OCP_USER_SDMA (1 << 1) + #define OCP_USER_DSP (1 << 2) + #define OCP_USER_IVA (1 << 3) + + /* omap_hwmod_ocp_if.flags bits */ + #define OCPIF_SWSUP_IDLE (1 << 0) + #define OCPIF_CAN_BURST (1 << 1) + + /* omap_hwmod_ocp_if._int_flags possibilities */ + #define _OCPIF_INT_FLAGS_REGISTERED (1 << 0) + + + /** + * struct omap_hwmod_ocp_if - OCP interface data + * @master: struct omap_hwmod that initiates OCP transactions on this link + * @slave: struct omap_hwmod that responds to OCP transactions on this link + * @addr: address space associated with this link + * @clk: interface clock: OMAP clock name + * @_clk: pointer to the interface struct clk (filled in at runtime) + * @fw: interface firewall data + * @width: OCP data width + * @user: initiators using this interface (see OCP_USER_* macros above) + * @flags: OCP interface flags (see OCPIF_* macros above) + * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above) + * + * It may also be useful to add a tag_cnt field for OCP2.x devices. + * + * Parameter names beginning with an underscore are managed internally by + * the omap_hwmod code and should not be set during initialization. + */ + struct omap_hwmod_ocp_if { + struct omap_hwmod *master; + struct omap_hwmod *slave; + struct omap_hwmod_addr_space *addr; + const char *clk; + struct clk *_clk; + union { + struct omap_hwmod_omap2_firewall omap2; + } fw; + u8 width; + u8 user; + u8 flags; + u8 _int_flags; + }; + + + /* Macros for use in struct omap_hwmod_sysconfig */ + + /* Flags for use in omap_hwmod_sysconfig.idlemodes */ + #define MASTER_STANDBY_SHIFT 4 + #define SLAVE_IDLE_SHIFT 0 + #define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT) + #define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT) + #define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT) + #define SIDLE_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT) + #define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT) + #define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT) + #define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT) + #define MSTANDBY_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT) + + /* omap_hwmod_sysconfig.sysc_flags capability flags */ + #define SYSC_HAS_AUTOIDLE (1 << 0) + #define SYSC_HAS_SOFTRESET (1 << 1) + #define SYSC_HAS_ENAWAKEUP (1 << 2) + #define SYSC_HAS_EMUFREE (1 << 3) + #define SYSC_HAS_CLOCKACTIVITY (1 << 4) + #define SYSC_HAS_SIDLEMODE (1 << 5) + #define SYSC_HAS_MIDLEMODE (1 << 6) + #define SYSS_HAS_RESET_STATUS (1 << 7) + #define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ + #define SYSC_HAS_RESET_STATUS (1 << 9) + #define SYSC_HAS_DMADISABLE (1 << 10) + + /* omap_hwmod_sysconfig.clockact flags */ + #define CLOCKACT_TEST_BOTH 0x0 + #define CLOCKACT_TEST_MAIN 0x1 + #define CLOCKACT_TEST_ICLK 0x2 + #define CLOCKACT_TEST_NONE 0x3 + + /** + * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets. + * @midle_shift: Offset of the midle bit + * @clkact_shift: Offset of the clockactivity bit + * @sidle_shift: Offset of the sidle bit + * @enwkup_shift: Offset of the enawakeup bit + * @srst_shift: Offset of the softreset bit + * @autoidle_shift: Offset of the autoidle bit + * @dmadisable_shift: Offset of the dmadisable bit + */ + struct omap_hwmod_sysc_fields { + u8 midle_shift; + u8 clkact_shift; + u8 sidle_shift; + u8 enwkup_shift; + u8 srst_shift; + u8 autoidle_shift; + u8 dmadisable_shift; + }; + + /** + * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data + * @rev_offs: IP block revision register offset (from module base addr) + * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) + * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) + * @srst_udelay: Delay needed after doing a softreset in usecs + * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} + * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported + * @clockact: the default value of the module CLOCKACTIVITY bits + * + * @clockact describes to the module which clocks are likely to be + * disabled when the PRCM issues its idle request to the module. Some + * modules have separate clockdomains for the interface clock and main + * functional clock, and can check whether they should acknowledge the + * idle request based on the internal module functionality that has + * been associated with the clocks marked in @clockact. This field is + * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below) + * + * @sysc_fields: structure containing the offset positions of various bits in + * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or + * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on + * whether the device ip is compliant with the original PRCM protocol + * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs. + * If the device follows a different scheme for the sysconfig register , + * then this field has to be populated with the correct offset structure. + */ + struct omap_hwmod_class_sysconfig { + u32 rev_offs; + u32 sysc_offs; + u32 syss_offs; + u16 sysc_flags; + struct omap_hwmod_sysc_fields *sysc_fields; + u8 srst_udelay; + u8 idlemodes; + u8 clockact; + }; + + /** + * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data + * @module_offs: PRCM submodule offset from the start of the PRM/CM + * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3) + * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs + * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3) + * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit + * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit + * + * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST, + * WKEN, GRPSEL registers. In an ideal world, no extra information + * would be needed for IDLEST information, but alas, there are some + * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit + * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST) + */ + struct omap_hwmod_omap2_prcm { + s16 module_offs; + u8 prcm_reg_id; + u8 module_bit; + u8 idlest_reg_id; + u8 idlest_idle_bit; + u8 idlest_stdby_bit; + }; + + /* + * Possible values for struct omap_hwmod_omap4_prcm.flags + * + * HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM + * module-level context loss register associated with them; this + * flag bit should be set in those cases + */ + #define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT (1 << 0) + + /** + * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data + * @clkctrl_reg: PRCM address of the clock control register + * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM + * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register + * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM + * @submodule_wkdep_bit: bit shift of the WKDEP range + * @flags: PRCM register capabilities for this IP block + * + * If @lostcontext_mask is not defined, context loss check code uses + * whole register without masking. @lostcontext_mask should only be + * defined in cases where @context_offs register is shared by two or + * more hwmods. + */ + struct omap_hwmod_omap4_prcm { + u16 clkctrl_offs; + u16 rstctrl_offs; + u16 rstst_offs; + u16 context_offs; + u32 lostcontext_mask; + u8 submodule_wkdep_bit; + u8 modulemode; + u8 flags; + }; + + + /* + * omap_hwmod.flags definitions + * + * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out + * of idle, rather than relying on module smart-idle + * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out + * of standby, rather than relying on module smart-standby + * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for + * SDRAM controller, etc. XXX probably belongs outside the main hwmod file + * XXX Should be HWMOD_SETUP_NO_RESET + * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM + * controller, etc. XXX probably belongs outside the main hwmod file + * XXX Should be HWMOD_SETUP_NO_IDLE + * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) + * when module is enabled, rather than the default, which is to + * enable autoidle + * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup + * HWMOD_NO_IDLEST: this module does not have idle status - this is the case + * only for few initiator modules on OMAP2 & 3. + * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset. + * This is needed for devices like DSS that require optional clocks enabled + * in order to complete the reset. Optional clocks will be disabled + * again after the reset. + * HWMOD_16BIT_REG: Module has 16bit registers ++ * HWMOD_EXT_OPT_MAIN_CLK: The only main functional clock source for ++ * this IP block comes from an off-chip source and is not always ++ * enabled. This prevents the hwmod code from being able to ++ * enable and reset the IP block early. XXX Eventually it should ++ * be possible to query the clock framework for this information. + */ + #define HWMOD_SWSUP_SIDLE (1 << 0) + #define HWMOD_SWSUP_MSTANDBY (1 << 1) + #define HWMOD_INIT_NO_RESET (1 << 2) + #define HWMOD_INIT_NO_IDLE (1 << 3) + #define HWMOD_NO_OCP_AUTOIDLE (1 << 4) + #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) + #define HWMOD_NO_IDLEST (1 << 6) + #define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7) + #define HWMOD_16BIT_REG (1 << 8) ++#define HWMOD_EXT_OPT_MAIN_CLK (1 << 9) + + /* + * omap_hwmod._int_flags definitions + * These are for internal use only and are managed by the omap_hwmod code. + * + * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module + * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP + * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached + * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) - + * causes the first call to _enable() to only update the pinmux + */ + #define _HWMOD_NO_MPU_PORT (1 << 0) + #define _HWMOD_WAKEUP_ENABLED (1 << 1) + #define _HWMOD_SYSCONFIG_LOADED (1 << 2) + #define _HWMOD_SKIP_ENABLE (1 << 3) + + /* + * omap_hwmod._state definitions + * + * INITIALIZED: reset (optionally), initialized, enabled, disabled + * (optionally) + * + * + */ + #define _HWMOD_STATE_UNKNOWN 0 + #define _HWMOD_STATE_REGISTERED 1 + #define _HWMOD_STATE_CLKS_INITED 2 + #define _HWMOD_STATE_INITIALIZED 3 + #define _HWMOD_STATE_ENABLED 4 + #define _HWMOD_STATE_IDLE 5 + #define _HWMOD_STATE_DISABLED 6 + + /** + * struct omap_hwmod_class - the type of an IP block + * @name: name of the hwmod_class + * @sysc: device SYSCONFIG/SYSSTATUS register data + * @rev: revision of the IP class + * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown + * @reset: ptr to fn to be executed in place of the standard hwmod reset fn + * + * Represent the class of a OMAP hardware "modules" (e.g. timer, + * smartreflex, gpio, uart...) + * + * @pre_shutdown is a function that will be run immediately before + * hwmod clocks are disabled, etc. It is intended for use for hwmods + * like the MPU watchdog, which cannot be disabled with the standard + * omap_hwmod_shutdown(). The function should return 0 upon success, + * or some negative error upon failure. Returning an error will cause + * omap_hwmod_shutdown() to abort the device shutdown and return an + * error. + * + * If @reset is defined, then the function it points to will be + * executed in place of the standard hwmod _reset() code in + * mach-omap2/omap_hwmod.c. This is needed for IP blocks which have + * unusual reset sequences - usually processor IP blocks like the IVA. + */ + struct omap_hwmod_class { + const char *name; + struct omap_hwmod_class_sysconfig *sysc; + u32 rev; + int (*pre_shutdown)(struct omap_hwmod *oh); + int (*reset)(struct omap_hwmod *oh); + }; + + /** + * struct omap_hwmod_link - internal structure linking hwmods with ocp_ifs + * @ocp_if: OCP interface structure record pointer + * @node: list_head pointing to next struct omap_hwmod_link in a list + */ + struct omap_hwmod_link { + struct omap_hwmod_ocp_if *ocp_if; + struct list_head node; + }; + + /** + * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) + * @name: name of the hwmod + * @class: struct omap_hwmod_class * to the class of this hwmod + * @od: struct omap_device currently associated with this hwmod (internal use) + * @mpu_irqs: ptr to an array of MPU IRQs + * @sdma_reqs: ptr to an array of System DMA request IDs + * @prcm: PRCM data pertaining to this hwmod + * @main_clk: main clock: OMAP clock name + * @_clk: pointer to the main struct clk (filled in at runtime) + * @opt_clks: other device clocks that drivers can request (0..*) + * @voltdm: pointer to voltage domain (filled in at runtime) + * @dev_attr: arbitrary device attributes that can be passed to the driver + * @_sysc_cache: internal-use hwmod flags + * @_mpu_rt_va: cached register target start address (internal use) + * @_mpu_port: cached MPU register target slave (internal use) + * @opt_clks_cnt: number of @opt_clks + * @master_cnt: number of @master entries + * @slaves_cnt: number of @slave entries + * @response_lat: device OCP response latency (in interface clock cycles) + * @_int_flags: internal-use hwmod flags + * @_state: internal-use hwmod state + * @_postsetup_state: internal-use state to leave the hwmod in after _setup() + * @flags: hwmod flags (documented below) + * @_lock: spinlock serializing operations on this hwmod + * @node: list node for hwmod list (internal use) + * + * @main_clk refers to this module's "main clock," which for our + * purposes is defined as "the functional clock needed for register + * accesses to complete." Modules may not have a main clock if the + * interface clock also serves as a main clock. + * + * Parameter names beginning with an underscore are managed internally by + * the omap_hwmod code and should not be set during initialization. + * + * @masters and @slaves are now deprecated. + */ + struct omap_hwmod { + const char *name; + struct omap_hwmod_class *class; + struct omap_device *od; + struct omap_hwmod_mux_info *mux; + struct omap_hwmod_irq_info *mpu_irqs; + struct omap_hwmod_dma_info *sdma_reqs; + struct omap_hwmod_rst_info *rst_lines; + union { + struct omap_hwmod_omap2_prcm omap2; + struct omap_hwmod_omap4_prcm omap4; + } prcm; + const char *main_clk; + struct clk *_clk; + struct omap_hwmod_opt_clk *opt_clks; + char *clkdm_name; + struct clockdomain *clkdm; + struct list_head master_ports; /* connect to *_IA */ + struct list_head slave_ports; /* connect to *_TA */ + void *dev_attr; + u32 _sysc_cache; + void __iomem *_mpu_rt_va; + spinlock_t _lock; + struct list_head node; + struct omap_hwmod_ocp_if *_mpu_port; + u16 flags; + u8 response_lat; + u8 rst_lines_cnt; + u8 opt_clks_cnt; + u8 masters_cnt; + u8 slaves_cnt; + u8 hwmods_cnt; + u8 _int_flags; + u8 _state; + u8 _postsetup_state; + }; + + struct omap_hwmod *omap_hwmod_lookup(const char *name); + int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), + void *data); + + int __init omap_hwmod_setup_one(const char *name); + + int omap_hwmod_enable(struct omap_hwmod *oh); + int omap_hwmod_idle(struct omap_hwmod *oh); + int omap_hwmod_shutdown(struct omap_hwmod *oh); + + int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name); + int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name); + int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name); + + int omap_hwmod_enable_clocks(struct omap_hwmod *oh); + int omap_hwmod_disable_clocks(struct omap_hwmod *oh); + + int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); + int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle); + + int omap_hwmod_reset(struct omap_hwmod *oh); + void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); + + void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs); + u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs); + int omap_hwmod_softreset(struct omap_hwmod *oh); + + int omap_hwmod_count_resources(struct omap_hwmod *oh); + int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); + int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res); + int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, + const char *name, struct resource *res); + + struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); + void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh); + + int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, + struct omap_hwmod *init_oh); + int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, + struct omap_hwmod *init_oh); + + int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); + int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); + + int omap_hwmod_for_each_by_class(const char *classname, + int (*fn)(struct omap_hwmod *oh, + void *user), + void *user); + + int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state); + int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh); + + int omap_hwmod_no_setup_reset(struct omap_hwmod *oh); + + int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx); + + extern void __init omap_hwmod_init(void); + + const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh); + + /* + * Chip variant-specific hwmod init routines - XXX should be converted + * to use initcalls once the initial boot ordering is straightened out + */ + extern int omap2420_hwmod_init(void); + extern int omap2430_hwmod_init(void); + extern int omap3xxx_hwmod_init(void); + extern int omap44xx_hwmod_init(void); + extern int am33xx_hwmod_init(void); + + extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); + + #endif diff --cc arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 0b1249e00398,224bbaf73f32..caf946dfd4a4 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@@ -21,18 -21,16 +21,17 @@@ #include #include #include +#include + #include + + #include - #include - #include - #include #include #include - #include + #include #include - #include - #include + #include "omap_hwmod.h" #include "omap_hwmod_common_data.h" #include "cm1_44xx.h" #include "cm2_44xx.h" diff --cc drivers/mmc/host/omap_hsmmc.c index e1f3c1135f93,9b24bd46aad3..bc5807873b2c --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@@ -37,11 -37,8 +37,9 @@@ #include #include #include +#include #include - #include - #include - #include + #include /* OMAP HSMMC Host Controller Registers */ #define OMAP_HSMMC_SYSSTATUS 0x0014 diff --cc drivers/tty/serial/atmel_serial.c index 1a8a2713dd95,5660ec2618a3..922e85aeb63a --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@@ -39,13 -39,13 +39,12 @@@ #include #include #include +#include + #include #include #include - #include -#include -- #ifdef CONFIG_ARM #include #include diff --cc include/linux/platform_data/mmc-omap.h index 000000000000,2bf6ea82ff94..2bf1b30cb5dc mode 000000,100644..100644 --- a/include/linux/platform_data/mmc-omap.h +++ b/include/linux/platform_data/mmc-omap.h @@@ -1,0 -1,150 +1,151 @@@ + /* + * MMC definitions for OMAP2 + * + * Copyright (C) 2006 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + #define OMAP_MMC_MAX_SLOTS 2 + + /* + * struct omap_mmc_dev_attr.flags possibilities + * + * OMAP_HSMMC_SUPPORTS_DUAL_VOLT: Some HSMMC controller instances can + * operate with either 1.8Vdc or 3.0Vdc card voltages; this flag + * should be set if this is the case. See for example Section 22.5.3 + * "MMC/SD/SDIO1 Bus Voltage Selection" of the OMAP34xx Multimedia + * Device Silicon Revision 3.1.x Revision ZR (July 2011) (SWPU223R). + * + * OMAP_HSMMC_BROKEN_MULTIBLOCK_READ: Multiple-block read transfers + * don't work correctly on some MMC controller instances on some + * OMAP3 SoCs; this flag should be set if this is the case. See + * for example Advisory 2.1.1.128 "MMC: Multiple Block Read + * Operation Issue" in _OMAP3530/3525/3515/3503 Silicon Errata_ + * Revision F (October 2010) (SPRZ278F). + */ + #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0) + #define OMAP_HSMMC_BROKEN_MULTIBLOCK_READ BIT(1) + + struct mmc_card; + + struct omap_mmc_dev_attr { + u8 flags; + }; + + struct omap_mmc_platform_data { + /* back-link to device */ + struct device *dev; + + /* number of slots per controller */ + unsigned nr_slots:2; + + /* set if your board has components or wiring that limits the + * maximum frequency on the MMC bus */ + unsigned int max_freq; + + /* switch the bus to a new slot */ + int (*switch_slot)(struct device *dev, int slot); + /* initialize board-specific MMC functionality, can be NULL if + * not supported */ + int (*init)(struct device *dev); + void (*cleanup)(struct device *dev); + void (*shutdown)(struct device *dev); + + /* To handle board related suspend/resume functionality for MMC */ + int (*suspend)(struct device *dev, int slot); + int (*resume)(struct device *dev, int slot); + + /* Return context loss count due to PM states changing */ + int (*get_context_loss_count)(struct device *dev); + + /* Integrating attributes from the omap_hwmod layer */ + u8 controller_flags; + + /* Register offset deviation */ + u16 reg_offset; + + struct omap_mmc_slot_data { + + /* + * 4/8 wires and any additional host capabilities + * need to OR'd all capabilities (ref. linux/mmc/host.h) + */ + u8 wires; /* Used for the MMC driver on omap1 and 2420 */ + u32 caps; /* Used for the MMC driver on 2430 and later */ + u32 pm_caps; /* PM capabilities of the mmc */ + + /* + * nomux means "standard" muxing is wrong on this board, and + * that board-specific code handled it before common init logic. + */ + unsigned nomux:1; + + /* switch pin can be for card detect (default) or card cover */ + unsigned cover:1; + + /* use the internal clock */ + unsigned internal_clock:1; + + /* nonremovable e.g. eMMC */ + unsigned nonremovable:1; + + /* Try to sleep or power off when possible */ + unsigned power_saving:1; + + /* If using power_saving and the MMC power is not to go off */ + unsigned no_off:1; + + /* eMMC does not handle power off when not in sleep state */ + unsigned no_regulator_off_init:1; + + /* Regulator off remapped to sleep */ + unsigned vcc_aux_disable_is_sleep:1; + + /* we can put the features above into this variable */ + #define HSMMC_HAS_PBIAS (1 << 0) + #define HSMMC_HAS_UPDATED_RESET (1 << 1) -#define MMC_OMAP7XX (1 << 2) -#define MMC_OMAP15XX (1 << 3) -#define MMC_OMAP16XX (1 << 4) ++#define HSMMC_HAS_HSPE_SUPPORT (1 << 2) ++#define MMC_OMAP7XX (1 << 3) ++#define MMC_OMAP15XX (1 << 4) ++#define MMC_OMAP16XX (1 << 5) + unsigned features; + + int switch_pin; /* gpio (card detect) */ + int gpio_wp; /* gpio (write protect) */ + + int (*set_bus_mode)(struct device *dev, int slot, int bus_mode); + int (*set_power)(struct device *dev, int slot, + int power_on, int vdd); + int (*get_ro)(struct device *dev, int slot); + void (*remux)(struct device *dev, int slot, int power_on); + /* Call back before enabling / disabling regulators */ + void (*before_set_reg)(struct device *dev, int slot, + int power_on, int vdd); + /* Call back after enabling / disabling regulators */ + void (*after_set_reg)(struct device *dev, int slot, + int power_on, int vdd); + /* if we have special card, init it using this callback */ + void (*init_card)(struct mmc_card *card); + + /* return MMC cover switch state, can be NULL if not supported. + * + * possible return values: + * 0 - closed + * 1 - open + */ + int (*get_cover_state)(struct device *dev, int slot); + + const char *name; + u32 ocr_mask; + + /* Card detection IRQs */ + int card_detect_irq; + int (*card_detect)(struct device *dev, int slot); + + unsigned int ban_openended:1; + + } slots[OMAP_MMC_MAX_SLOTS]; + };