From: Larry Finger Date: Thu, 22 Aug 2013 03:33:55 +0000 (-0500) Subject: staging: r8188eu: Add files for new driver - part 13 X-Git-Tag: MMI-PSA29.97-13-9~13778^2~156 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=7ef8ded0cfdb690e37581af85eea35fa67cdb38d;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git staging: r8188eu: Add files for new driver - part 13 This commit adds files hal/odm_RTL8188E.c, hal/odm_RegConfig8188E.c, hal/rtl8188e_cmd.c, and hal/rtl8188e_dm.c. Signed-off-by: Larry Finger Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/rtl8188eu/hal/odm_RTL8188E.c b/drivers/staging/rtl8188eu/hal/odm_RTL8188E.c new file mode 100644 index 000000000000..58410f3e5316 --- /dev/null +++ b/drivers/staging/rtl8188eu/hal/odm_RTL8188E.c @@ -0,0 +1,399 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "odm_precomp.h" + +void ODM_DIG_LowerBound_88E(struct odm_dm_struct *dm_odm) +{ + struct rtw_dig *pDM_DigTable = &dm_odm->DM_DigTable; + + if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) { + pDM_DigTable->rx_gain_range_min = (u8) pDM_DigTable->AntDiv_RSSI_max; + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d\n", pDM_DigTable->AntDiv_RSSI_max)); + } + /* If only one Entry connected */ +} + +static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm) +{ + u32 value32; + + if (*(dm_odm->mp_mode) == 1) { + dm_odm->AntDivType = CGCS_RX_SW_ANTDIV; + ODM_SetBBReg(dm_odm, ODM_REG_IGI_A_11N, BIT7, 0); /* disable HW AntDiv */ + ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* 1:CG, 0:CS */ + return; + } + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit()\n")); + + /* MAC Setting */ + value32 = ODM_GetMACReg(dm_odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); + ODM_SetMACReg(dm_odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + /* Pin Settings */ + ODM_SetBBReg(dm_odm, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ + ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */ + ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT22, 1); /* Regb2c[22]=1'b0 disable CS/CG switch */ + ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */ + /* OFDM Settings */ + ODM_SetBBReg(dm_odm, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); + /* CCK Settings */ + ODM_SetBBReg(dm_odm, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */ + ODM_SetBBReg(dm_odm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */ + ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT); + ODM_SetBBReg(dm_odm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); /* antenna mapping table */ +} + +static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm) +{ + u32 value32; + + if (*(dm_odm->mp_mode) == 1) { + dm_odm->AntDivType = CGCS_RX_SW_ANTDIV; + ODM_SetBBReg(dm_odm, ODM_REG_IGI_A_11N, BIT7, 0); /* disable HW AntDiv */ + ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, 0); /* Default RX (0/1) */ + return; + } + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit()\n")); + + /* MAC Setting */ + value32 = ODM_GetMACReg(dm_odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); + ODM_SetMACReg(dm_odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + /* Pin Settings */ + ODM_SetBBReg(dm_odm, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ + ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */ + ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */ + ODM_SetBBReg(dm_odm, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */ + /* OFDM Settings */ + ODM_SetBBReg(dm_odm, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); + /* CCK Settings */ + ODM_SetBBReg(dm_odm, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */ + ODM_SetBBReg(dm_odm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */ + /* Tx Settings */ + ODM_SetBBReg(dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */ + ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT); + + /* antenna mapping table */ + if (!dm_odm->bIsMPChip) { /* testchip */ + ODM_SetBBReg(dm_odm, ODM_REG_RX_DEFUALT_A_11N, BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */ + ODM_SetBBReg(dm_odm, ODM_REG_RX_DEFUALT_A_11N, BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */ + } else { /* MPchip */ + ODM_SetBBReg(dm_odm, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */ + } +} + +static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm) +{ + u32 value32, i; + struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; + u32 AntCombination = 2; + + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit()\n")); + + if (*(dm_odm->mp_mode) == 1) { + ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("dm_odm->AntDivType: %d\n", dm_odm->AntDivType)); + return; + } + + for (i = 0; i < 6; i++) { + dm_fat_tbl->Bssid[i] = 0; + dm_fat_tbl->antSumRSSI[i] = 0; + dm_fat_tbl->antRSSIcnt[i] = 0; + dm_fat_tbl->antAveRSSI[i] = 0; + } + dm_fat_tbl->TrainIdx = 0; + dm_fat_tbl->FAT_State = FAT_NORMAL_STATE; + + /* MAC Setting */ + value32 = ODM_GetMACReg(dm_odm, 0x4c, bMaskDWord); + ODM_SetMACReg(dm_odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + value32 = ODM_GetMACReg(dm_odm, 0x7B4, bMaskDWord); + ODM_SetMACReg(dm_odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */ + + /* Match MAC ADDR */ + ODM_SetMACReg(dm_odm, 0x7b4, 0xFFFF, 0); + ODM_SetMACReg(dm_odm, 0x7b0, bMaskDWord, 0); + + ODM_SetBBReg(dm_odm, 0x870, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ + ODM_SetBBReg(dm_odm, 0x864, BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */ + ODM_SetBBReg(dm_odm, 0xb2c, BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */ + ODM_SetBBReg(dm_odm, 0xb2c, BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */ + ODM_SetBBReg(dm_odm, 0xca4, bMaskDWord, 0x000000a0); + + /* antenna mapping table */ + if (AntCombination == 2) { + if (!dm_odm->bIsMPChip) { /* testchip */ + ODM_SetBBReg(dm_odm, 0x858, BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */ + ODM_SetBBReg(dm_odm, 0x858, BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */ + } else { /* MPchip */ + ODM_SetBBReg(dm_odm, 0x914, bMaskByte0, 1); + ODM_SetBBReg(dm_odm, 0x914, bMaskByte1, 2); + } + } else if (AntCombination == 7) { + if (!dm_odm->bIsMPChip) { /* testchip */ + ODM_SetBBReg(dm_odm, 0x858, BIT10|BIT9|BIT8, 0); /* Reg858[10:8]=3'b000 */ + ODM_SetBBReg(dm_odm, 0x858, BIT13|BIT12|BIT11, 1); /* Reg858[13:11]=3'b001 */ + ODM_SetBBReg(dm_odm, 0x878, BIT16, 0); + ODM_SetBBReg(dm_odm, 0x858, BIT15|BIT14, 2); /* Reg878[0],Reg858[14:15])=3'b010 */ + ODM_SetBBReg(dm_odm, 0x878, BIT19|BIT18|BIT17, 3);/* Reg878[3:1]=3b'011 */ + ODM_SetBBReg(dm_odm, 0x878, BIT22|BIT21|BIT20, 4);/* Reg878[6:4]=3b'100 */ + ODM_SetBBReg(dm_odm, 0x878, BIT25|BIT24|BIT23, 5);/* Reg878[9:7]=3b'101 */ + ODM_SetBBReg(dm_odm, 0x878, BIT28|BIT27|BIT26, 6);/* Reg878[12:10]=3b'110 */ + ODM_SetBBReg(dm_odm, 0x878, BIT31|BIT30|BIT29, 7);/* Reg878[15:13]=3b'111 */ + } else { /* MPchip */ + ODM_SetBBReg(dm_odm, 0x914, bMaskByte0, 0); + ODM_SetBBReg(dm_odm, 0x914, bMaskByte1, 1); + ODM_SetBBReg(dm_odm, 0x914, bMaskByte2, 2); + ODM_SetBBReg(dm_odm, 0x914, bMaskByte3, 3); + ODM_SetBBReg(dm_odm, 0x918, bMaskByte0, 4); + ODM_SetBBReg(dm_odm, 0x918, bMaskByte1, 5); + ODM_SetBBReg(dm_odm, 0x918, bMaskByte2, 6); + ODM_SetBBReg(dm_odm, 0x918, bMaskByte3, 7); + } + } + + /* Default Ant Setting when no fast training */ + ODM_SetBBReg(dm_odm, 0x80c, BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */ + ODM_SetBBReg(dm_odm, 0x864, BIT5|BIT4|BIT3, 0); /* Default RX */ + ODM_SetBBReg(dm_odm, 0x864, BIT8|BIT7|BIT6, 1); /* Optional RX */ + + /* Enter Traing state */ + ODM_SetBBReg(dm_odm, 0x864, BIT2|BIT1|BIT0, (AntCombination-1)); /* Reg864[2:0]=3'd6 ant combination=reg864[2:0]+1 */ + ODM_SetBBReg(dm_odm, 0xc50, BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */ +} + +void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm) +{ + if (dm_odm->SupportICType != ODM_RTL8188E) + return; + + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->AntDivType=%d\n", dm_odm->AntDivType)); + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->bIsMPChip=%s\n", (dm_odm->bIsMPChip ? "true" : "false"))); + + if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) + odm_RX_HWAntDivInit(dm_odm); + else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_TRX_HWAntDivInit(dm_odm); + else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV) + odm_FastAntTrainingInit(dm_odm); +} + +void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant) +{ + struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; + u32 DefaultAnt, OptionalAnt; + + if (dm_fat_tbl->RxIdleAnt != Ant) { + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Update Rx Idle Ant\n")); + if (Ant == MAIN_ANT) { + DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; + OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; + } else { + DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX; + OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX; + } + + if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) { + ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */ + ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */ + ODM_SetBBReg(dm_odm, ODM_REG_ANTSEL_CTRL_11N, BIT14|BIT13|BIT12, DefaultAnt); /* Default TX */ + ODM_SetMACReg(dm_odm, ODM_REG_RESP_TX_11N, BIT6|BIT7, DefaultAnt); /* Resp Tx */ + } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) { + ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */ + ODM_SetBBReg(dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */ + } + } + dm_fat_tbl->RxIdleAnt = Ant; + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RxIdleAnt=%s\n", (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + pr_info("RxIdleAnt=%s\n", (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); +} + +static void odm_UpdateTxAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant, u32 MacId) +{ + struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; + u8 TargetAnt; + + if (Ant == MAIN_ANT) + TargetAnt = MAIN_ANT_CG_TRX; + else + TargetAnt = AUX_ANT_CG_TRX; + dm_fat_tbl->antsel_a[MacId] = TargetAnt&BIT0; + dm_fat_tbl->antsel_b[MacId] = (TargetAnt&BIT1)>>1; + dm_fat_tbl->antsel_c[MacId] = (TargetAnt&BIT2)>>2; + + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("Tx from TxInfo, TargetAnt=%s\n", + (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("antsel_tr_mux=3'b%d%d%d\n", + dm_fat_tbl->antsel_c[MacId], dm_fat_tbl->antsel_b[MacId], dm_fat_tbl->antsel_a[MacId])); +} + +void ODM_SetTxAntByTxInfo_88E(struct odm_dm_struct *dm_odm, u8 *pDesc, u8 macId) +{ + struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; + + if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)) { + SET_TX_DESC_ANTSEL_A_88E(pDesc, dm_fat_tbl->antsel_a[macId]); + SET_TX_DESC_ANTSEL_B_88E(pDesc, dm_fat_tbl->antsel_b[macId]); + SET_TX_DESC_ANTSEL_C_88E(pDesc, dm_fat_tbl->antsel_c[macId]); + } +} + +void ODM_AntselStatistics_88E(struct odm_dm_struct *dm_odm, u8 antsel_tr_mux, u32 MacId, u8 RxPWDBAll) +{ + struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; + if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) { + if (antsel_tr_mux == MAIN_ANT_CG_TRX) { + dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll; + dm_fat_tbl->MainAnt_Cnt[MacId]++; + } else { + dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll; + dm_fat_tbl->AuxAnt_Cnt[MacId]++; + } + } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) { + if (antsel_tr_mux == MAIN_ANT_CGCS_RX) { + dm_fat_tbl->MainAnt_Sum[MacId] += RxPWDBAll; + dm_fat_tbl->MainAnt_Cnt[MacId]++; + } else { + dm_fat_tbl->AuxAnt_Sum[MacId] += RxPWDBAll; + dm_fat_tbl->AuxAnt_Cnt[MacId]++; + } + } +} + +static void odm_HWAntDiv(struct odm_dm_struct *dm_odm) +{ + u32 i, MinRSSI = 0xFF, AntDivMaxRSSI = 0, MaxRSSI = 0, LocalMinRSSI, LocalMaxRSSI; + u32 Main_RSSI, Aux_RSSI; + u8 RxIdleAnt = 0, TargetAnt = 7; + struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; + struct rtw_dig *pDM_DigTable = &dm_odm->DM_DigTable; + struct sta_info *pEntry; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + pEntry = dm_odm->pODM_StaInfo[i]; + if (IS_STA_VALID(pEntry)) { + /* 2 Caculate RSSI per Antenna */ + Main_RSSI = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ? (dm_fat_tbl->MainAnt_Sum[i]/dm_fat_tbl->MainAnt_Cnt[i]) : 0; + Aux_RSSI = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ? (dm_fat_tbl->AuxAnt_Sum[i]/dm_fat_tbl->AuxAnt_Cnt[i]) : 0; + TargetAnt = (Main_RSSI >= Aux_RSSI) ? MAIN_ANT : AUX_ANT; + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("MacID=%d, MainAnt_Sum=%d, MainAnt_Cnt=%d\n", + i, dm_fat_tbl->MainAnt_Sum[i], + dm_fat_tbl->MainAnt_Cnt[i])); + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("MacID=%d, AuxAnt_Sum=%d, AuxAnt_Cnt=%d\n", + i, dm_fat_tbl->AuxAnt_Sum[i], dm_fat_tbl->AuxAnt_Cnt[i])); + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("MacID=%d, Main_RSSI= %d, Aux_RSSI= %d\n", + i, Main_RSSI, Aux_RSSI)); + /* 2 Select MaxRSSI for DIG */ + LocalMaxRSSI = (Main_RSSI > Aux_RSSI) ? Main_RSSI : Aux_RSSI; + if ((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40)) + AntDivMaxRSSI = LocalMaxRSSI; + if (LocalMaxRSSI > MaxRSSI) + MaxRSSI = LocalMaxRSSI; + + /* 2 Select RX Idle Antenna */ + if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0)) + Main_RSSI = Aux_RSSI; + else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0)) + Aux_RSSI = Main_RSSI; + + LocalMinRSSI = (Main_RSSI > Aux_RSSI) ? Aux_RSSI : Main_RSSI; + if (LocalMinRSSI < MinRSSI) { + MinRSSI = LocalMinRSSI; + RxIdleAnt = TargetAnt; + } + /* 2 Select TRX Antenna */ + if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_UpdateTxAnt_88E(dm_odm, TargetAnt, i); + } + dm_fat_tbl->MainAnt_Sum[i] = 0; + dm_fat_tbl->AuxAnt_Sum[i] = 0; + dm_fat_tbl->MainAnt_Cnt[i] = 0; + dm_fat_tbl->AuxAnt_Cnt[i] = 0; + } + + /* 2 Set RX Idle Antenna */ + ODM_UpdateRxIdleAnt_88E(dm_odm, RxIdleAnt); + + pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI; + pDM_DigTable->RSSI_max = MaxRSSI; +} + +void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm) +{ + struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; + if ((dm_odm->SupportICType != ODM_RTL8188E) || (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV))) + return; + if (!dm_odm->bLinked) { + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E(): No Link.\n")); + if (dm_fat_tbl->bBecomeLinked) { + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn off HW AntDiv\n")); + ODM_SetBBReg(dm_odm, ODM_REG_IGI_A_11N, BIT7, 0); /* RegC50[7]=1'b1 enable HW AntDiv */ + ODM_SetBBReg(dm_odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 0); /* Enable CCK AntDiv */ + if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) + ODM_SetBBReg(dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */ + dm_fat_tbl->bBecomeLinked = dm_odm->bLinked; + } + return; + } else { + if (!dm_fat_tbl->bBecomeLinked) { + ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Turn on HW AntDiv\n")); + /* Because HW AntDiv is disabled before Link, we enable HW AntDiv after link */ + ODM_SetBBReg(dm_odm, ODM_REG_IGI_A_11N, BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */ + ODM_SetBBReg(dm_odm, ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1); /* Enable CCK AntDiv */ + if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) + ODM_SetBBReg(dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */ + dm_fat_tbl->bBecomeLinked = dm_odm->bLinked; + } + } + if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) || (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)) + odm_HWAntDiv(dm_odm); +} + +/* 3============================================================ */ +/* 3 Dynamic Primary CCA */ +/* 3============================================================ */ + +void odm_PrimaryCCA_Init(struct odm_dm_struct *dm_odm) +{ + struct dyn_primary_cca *PrimaryCCA = &(dm_odm->DM_PriCCA); + + PrimaryCCA->DupRTS_flag = 0; + PrimaryCCA->intf_flag = 0; + PrimaryCCA->intf_type = 0; + PrimaryCCA->Monitor_flag = 0; + PrimaryCCA->PriCCA_flag = 0; +} + +bool ODM_DynamicPrimaryCCA_DupRTS(struct odm_dm_struct *dm_odm) +{ + struct dyn_primary_cca *PrimaryCCA = &(dm_odm->DM_PriCCA); + + return PrimaryCCA->DupRTS_flag; +} + +void odm_DynamicPrimaryCCA(struct odm_dm_struct *dm_odm) +{ + return; +} diff --git a/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c b/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c new file mode 100644 index 000000000000..18c0533fbd01 --- /dev/null +++ b/drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c @@ -0,0 +1,130 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "odm_precomp.h" + +void odm_ConfigRFReg_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, + u32 Data, enum ODM_RF_RADIO_PATH RF_PATH, + u32 RegAddr) +{ + if (Addr == 0xffe) { + ODM_sleep_ms(50); + } else if (Addr == 0xfd) { + ODM_delay_ms(5); + } else if (Addr == 0xfc) { + ODM_delay_ms(1); + } else if (Addr == 0xfb) { + ODM_delay_us(50); + } else if (Addr == 0xfa) { + ODM_delay_us(5); + } else if (Addr == 0xf9) { + ODM_delay_us(1); + } else { + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + } +} + +void odm_ConfigRF_RadioA_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data) +{ + u32 content = 0x1000; /* RF_Content: radioa_txt */ + u32 maskforPhySet = (u32)(content&0xE000); + + odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +void odm_ConfigRF_RadioB_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Data) +{ + u32 content = 0x1001; /* RF_Content: radiob_txt */ + u32 maskforPhySet = (u32)(content&0xE000); + + odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); +} + +void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data) +{ + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", + Addr, Data)); +} + +void odm_ConfigBB_PHY_REG_PG_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, + u32 Bitmask, u32 Data) +{ + if (Addr == 0xfe) { + ODM_sleep_ms(50); + } else if (Addr == 0xfd) { + ODM_delay_ms(5); + } else if (Addr == 0xfc) { + ODM_delay_ms(1); + } else if (Addr == 0xfb) { + ODM_delay_us(50); + } else if (Addr == 0xfa) { + ODM_delay_us(5); + } else if (Addr == 0xf9) { + ODM_delay_us(1); + } else{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", + Addr, Bitmask, Data)); + storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data); + } +} + +void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data) +{ + if (Addr == 0xfe) { + ODM_sleep_ms(50); + } else if (Addr == 0xfd) { + ODM_delay_ms(5); + } else if (Addr == 0xfc) { + ODM_delay_ms(1); + } else if (Addr == 0xfb) { + ODM_delay_us(50); + } else if (Addr == 0xfa) { + ODM_delay_us(5); + } else if (Addr == 0xf9) { + ODM_delay_us(1); + } else { + if (Addr == 0xa24) + pDM_Odm->RFCalibrateInfo.RegA24 = Data; + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", + Addr, Data)); + } +} diff --git a/drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c b/drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c new file mode 100644 index 000000000000..8c8587754517 --- /dev/null +++ b/drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c @@ -0,0 +1,779 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8188E_CMD_C_ + +#include +#include +#include +#include +#include +#include + +#include + +#define RTL88E_MAX_H2C_BOX_NUMS 4 +#define RTL88E_MAX_CMD_LEN 7 +#define RTL88E_MESSAGE_BOX_SIZE 4 +#define RTL88E_EX_MESSAGE_BOX_SIZE 4 + +static u8 _is_fw_read_cmd_down(struct adapter *adapt, u8 msgbox_num) +{ + u8 read_down = false; + int retry_cnts = 100; + + u8 valid; + + do { + valid = rtw_read8(adapt, REG_HMETFR) & BIT(msgbox_num); + if (0 == valid) + read_down = true; + } while ((!read_down) && (retry_cnts--)); + + return read_down; +} + +/***************************************** +* H2C Msg format : +* 0x1DF - 0x1D0 +*| 31 - 8 | 7-5 4 - 0 | +*| h2c_msg |Class_ID CMD_ID | +* +* Extend 0x1FF - 0x1F0 +*|31 - 0 | +*|ext_msg| +******************************************/ +static s32 FillH2CCmd_88E(struct adapter *adapt, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer) +{ + u8 bcmd_down = false; + s32 retry_cnts = 100; + u8 h2c_box_num; + u32 msgbox_addr; + u32 msgbox_ex_addr; + struct hal_data_8188e *haldata = GET_HAL_DATA(adapt); + u8 cmd_idx, ext_cmd_len; + u32 h2c_cmd = 0; + u32 h2c_cmd_ex = 0; + s32 ret = _FAIL; + +_func_enter_; + + if (!adapt->bFWReady) { + DBG_88E("FillH2CCmd_88E(): return H2C cmd because fw is not ready\n"); + return ret; + } + + if (!pCmdBuffer) + goto exit; + if (CmdLen > RTL88E_MAX_CMD_LEN) + goto exit; + if (adapt->bSurpriseRemoved) + goto exit; + + /* pay attention to if race condition happened in H2C cmd setting. */ + do { + h2c_box_num = haldata->LastHMEBoxNum; + + if (!_is_fw_read_cmd_down(adapt, h2c_box_num)) { + DBG_88E(" fw read cmd failed...\n"); + goto exit; + } + + *(u8 *)(&h2c_cmd) = ElementID; + + if (CmdLen <= 3) { + memcpy((u8 *)(&h2c_cmd)+1, pCmdBuffer, CmdLen); + } else { + memcpy((u8 *)(&h2c_cmd)+1, pCmdBuffer, 3); + ext_cmd_len = CmdLen-3; + memcpy((u8 *)(&h2c_cmd_ex), pCmdBuffer+3, ext_cmd_len); + + /* Write Ext command */ + msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num * RTL88E_EX_MESSAGE_BOX_SIZE); + for (cmd_idx = 0; cmd_idx < ext_cmd_len; cmd_idx++) { + rtw_write8(adapt, msgbox_ex_addr+cmd_idx, *((u8 *)(&h2c_cmd_ex)+cmd_idx)); + } + } + /* Write command */ + msgbox_addr = REG_HMEBOX_0 + (h2c_box_num * RTL88E_MESSAGE_BOX_SIZE); + for (cmd_idx = 0; cmd_idx < RTL88E_MESSAGE_BOX_SIZE; cmd_idx++) { + rtw_write8(adapt, msgbox_addr+cmd_idx, *((u8 *)(&h2c_cmd)+cmd_idx)); + } + bcmd_down = true; + + haldata->LastHMEBoxNum = (h2c_box_num+1) % RTL88E_MAX_H2C_BOX_NUMS; + + } while ((!bcmd_down) && (retry_cnts--)); + + ret = _SUCCESS; + +exit: + +_func_exit_; + + return ret; +} + +u8 rtl8188e_set_rssi_cmd(struct adapter *adapt, u8 *param) +{ + u8 res = _SUCCESS; + struct hal_data_8188e *haldata = GET_HAL_DATA(adapt); +_func_enter_; + + if (haldata->fw_ractrl) { + ; + } else { + DBG_88E("==>%s fw dont support RA\n", __func__); + res = _FAIL; + } + +_func_exit_; + + return res; +} + +u8 rtl8188e_set_raid_cmd(struct adapter *adapt, u32 mask) +{ + u8 buf[3]; + u8 res = _SUCCESS; + struct hal_data_8188e *haldata = GET_HAL_DATA(adapt); + +_func_enter_; + if (haldata->fw_ractrl) { + __le32 lmask; + + _rtw_memset(buf, 0, 3); + lmask = cpu_to_le32(mask); + memcpy(buf, &lmask, 3); + + FillH2CCmd_88E(adapt, H2C_DM_MACID_CFG, 3, buf); + } else { + DBG_88E("==>%s fw dont support RA\n", __func__); + res = _FAIL; + } + +_func_exit_; + + return res; +} + +/* bitmap[0:27] = tx_rate_bitmap */ +/* bitmap[28:31]= Rate Adaptive id */ +/* arg[0:4] = macid */ +/* arg[5] = Short GI */ +void rtl8188e_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi_level) +{ + struct hal_data_8188e *haldata = GET_HAL_DATA(pAdapter); + + u8 macid, init_rate, raid, shortGIrate = false; + + macid = arg&0x1f; + + raid = (bitmap>>28) & 0x0f; + bitmap &= 0x0fffffff; + + if (rssi_level != DM_RATR_STA_INIT) + bitmap = ODM_Get_Rate_Bitmap(&haldata->odmpriv, macid, bitmap, rssi_level); + + bitmap |= ((raid<<28)&0xf0000000); + + init_rate = get_highest_rate_idx(bitmap&0x0fffffff)&0x3f; + + shortGIrate = (arg&BIT(5)) ? true : false; + + if (shortGIrate) + init_rate |= BIT(6); + + raid = (bitmap>>28) & 0x0f; + + bitmap &= 0x0fffffff; + + DBG_88E("%s=> mac_id:%d, raid:%d, ra_bitmap=0x%x, shortGIrate=0x%02x\n", + __func__, macid, raid, bitmap, shortGIrate); + + ODM_RA_UpdateRateInfo_8188E(&(haldata->odmpriv), macid, raid, bitmap, shortGIrate); +} + +void rtl8188e_set_FwPwrMode_cmd(struct adapter *adapt, u8 Mode) +{ + struct setpwrmode_parm H2CSetPwrMode; + struct pwrctrl_priv *pwrpriv = &adapt->pwrctrlpriv; + u8 RLBM = 0; /* 0:Min, 1:Max, 2:User define */ +_func_enter_; + + DBG_88E("%s: Mode=%d SmartPS=%d UAPSD=%d\n", __func__, + Mode, pwrpriv->smart_ps, adapt->registrypriv.uapsd_enable); + + switch (Mode) { + case PS_MODE_ACTIVE: + H2CSetPwrMode.Mode = 0; + break; + case PS_MODE_MIN: + H2CSetPwrMode.Mode = 1; + break; + case PS_MODE_MAX: + RLBM = 1; + H2CSetPwrMode.Mode = 1; + break; + case PS_MODE_DTIM: + RLBM = 2; + H2CSetPwrMode.Mode = 1; + break; + case PS_MODE_UAPSD_WMM: + H2CSetPwrMode.Mode = 2; + break; + default: + H2CSetPwrMode.Mode = 0; + break; + } + + H2CSetPwrMode.SmartPS_RLBM = (((pwrpriv->smart_ps<<4)&0xf0) | (RLBM & 0x0f)); + + H2CSetPwrMode.AwakeInterval = 1; + + H2CSetPwrMode.bAllQueueUAPSD = adapt->registrypriv.uapsd_enable; + + if (Mode > 0) + H2CSetPwrMode.PwrState = 0x00;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */ + else + H2CSetPwrMode.PwrState = 0x0C;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */ + + FillH2CCmd_88E(adapt, H2C_PS_PWR_MODE, sizeof(H2CSetPwrMode), (u8 *)&H2CSetPwrMode); + +_func_exit_; +} + +void rtl8188e_set_FwMediaStatus_cmd(struct adapter *adapt, __le16 mstatus_rpt) +{ + u8 opmode, macid; + u16 mst_rpt = le16_to_cpu(mstatus_rpt); + opmode = (u8) mst_rpt; + macid = (u8)(mst_rpt >> 8); + + DBG_88E("### %s: MStatus=%x MACID=%d\n", __func__, opmode, macid); + FillH2CCmd_88E(adapt, H2C_COM_MEDIA_STATUS_RPT, sizeof(mst_rpt), (u8 *)&mst_rpt); +} + +static void ConstructBeacon(struct adapter *adapt, u8 *pframe, u32 *pLength) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 rate_len, pktlen; + struct mlme_ext_priv *pmlmeext = &(adapt->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wlan_bssid_ex *cur_network = &(pmlmeinfo->network); + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + memcpy(pwlanhdr->addr2, myid(&(adapt->eeprompriv)), ETH_ALEN); + memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); + + SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); + SetFrameSubType(pframe, WIFI_BEACON); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /* timestamp will be inserted by hardware */ + pframe += 8; + pktlen += 8; + + /* beacon interval: 2 bytes */ + memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pktlen += 2; + + /* capability info: 2 bytes */ + memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pktlen += 2; + + if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) { + pktlen += cur_network->IELength - sizeof(struct ndis_802_11_fixed_ie); + memcpy(pframe, cur_network->IEs+sizeof(struct ndis_802_11_fixed_ie), pktlen); + + goto _ConstructBeacon; + } + + /* below for ad-hoc mode */ + + /* SSID */ + pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen); + + /* supported rates... */ + rate_len = rtw_get_rateset_len(cur_network->SupportedRates); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen); + + /* DS parameter set */ + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen); + + if ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) { + u32 ATIMWindow; + /* IBSS Parameter Set... */ + ATIMWindow = 0; + pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen); + } + + /* todo: ERP IE */ + + /* EXTERNDED SUPPORTED RATE */ + if (rate_len > 8) + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen); + + /* todo:HT for adhoc */ + +_ConstructBeacon: + + if ((pktlen + TXDESC_SIZE) > 512) { + DBG_88E("beacon frame too large\n"); + return; + } + + *pLength = pktlen; +} + +static void ConstructPSPoll(struct adapter *adapt, u8 *pframe, u32 *pLength) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + struct mlme_ext_priv *pmlmeext = &(adapt->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u16 *fctrl; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + /* Frame control. */ + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + SetPwrMgt(fctrl); + SetFrameSubType(pframe, WIFI_PSPOLL); + + /* AID. */ + SetDuration(pframe, (pmlmeinfo->aid | 0xc000)); + + /* BSSID. */ + memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + /* TA. */ + memcpy(pwlanhdr->addr2, myid(&(adapt->eeprompriv)), ETH_ALEN); + + *pLength = 16; +} + +static void ConstructNullFunctionData(struct adapter *adapt, u8 *pframe, + u32 *pLength, + u8 *StaAddr, + u8 bQoS, + u8 AC, + u8 bEosp, + u8 bForcePowerSave) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 pktlen; + struct mlme_priv *pmlmepriv = &adapt->mlmepriv; + struct wlan_network *cur_network = &pmlmepriv->cur_network; + struct mlme_ext_priv *pmlmeext = &(adapt->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + if (bForcePowerSave) + SetPwrMgt(fctrl); + + switch (cur_network->network.InfrastructureMode) { + case Ndis802_11Infrastructure: + SetToDs(fctrl); + memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + memcpy(pwlanhdr->addr2, myid(&(adapt->eeprompriv)), ETH_ALEN); + memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN); + break; + case Ndis802_11APMode: + SetFrDs(fctrl); + memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + memcpy(pwlanhdr->addr3, myid(&(adapt->eeprompriv)), ETH_ALEN); + break; + case Ndis802_11IBSS: + default: + memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + memcpy(pwlanhdr->addr2, myid(&(adapt->eeprompriv)), ETH_ALEN); + memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + break; + } + + SetSeqNum(pwlanhdr, 0); + + if (bQoS) { + struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; + + SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); + + pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe; + SetPriority(&pwlanqoshdr->qc, AC); + SetEOSP(&pwlanqoshdr->qc, bEosp); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); + } else { + SetFrameSubType(pframe, WIFI_DATA_NULL); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + } + + *pLength = pktlen; +} + +static void ConstructProbeRsp(struct adapter *adapt, u8 *pframe, u32 *pLength, u8 *StaAddr, bool bHideSSID) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u8 *mac, *bssid; + u32 pktlen; + struct mlme_ext_priv *pmlmeext = &(adapt->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wlan_bssid_ex *cur_network = &(pmlmeinfo->network); + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + mac = myid(&(adapt->eeprompriv)); + bssid = cur_network->MacAddress; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + memcpy(pwlanhdr->addr2, mac, ETH_ALEN); + memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); + + SetSeqNum(pwlanhdr, 0); + SetFrameSubType(fctrl, WIFI_PROBERSP); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pframe += pktlen; + + if (cur_network->IELength > MAX_IE_SZ) + return; + + memcpy(pframe, cur_network->IEs, cur_network->IELength); + pframe += cur_network->IELength; + pktlen += cur_network->IELength; + + *pLength = pktlen; +} + +/* To check if reserved page content is destroyed by beacon beacuse beacon is too large. */ +/* 2010.06.23. Added by tynli. */ +void CheckFwRsvdPageContent(struct adapter *Adapter) +{ +} + +/* */ +/* Description: Fill the reserved packets that FW will use to RSVD page. */ +/* Now we just send 4 types packet to rsvd page. */ +/* (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. */ +/* Input: */ +/* bDLFinished - false: At the first time we will send all the packets as a large packet to Hw, */ +/* so we need to set the packet length to total lengh. */ +/* true: At the second time, we should send the first packet (default:beacon) */ +/* to Hw again and set the lengh in descriptor to the real beacon lengh. */ +/* 2009.10.15 by tynli. */ +static void SetFwRsvdPagePkt(struct adapter *adapt, bool bDLFinished) +{ + struct hal_data_8188e *haldata; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct xmit_priv *pxmitpriv; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + u32 BeaconLength = 0, ProbeRspLength = 0, PSPollLength; + u32 NullDataLength, QosNullLength; + u8 *ReservedPagePacket; + u8 PageNum, PageNeed, TxDescLen; + u16 BufIndex; + u32 TotalPacketLen; + struct rsvdpage_loc RsvdPageLoc; + + DBG_88E("%s\n", __func__); + ReservedPagePacket = (u8 *)rtw_zmalloc(1000); + if (ReservedPagePacket == NULL) { + DBG_88E("%s: alloc ReservedPagePacket fail!\n", __func__); + return; + } + + haldata = GET_HAL_DATA(adapt); + pxmitpriv = &adapt->xmitpriv; + pmlmeext = &adapt->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + TxDescLen = TXDESC_SIZE; + PageNum = 0; + + /* 3 (1) beacon * 2 pages */ + BufIndex = TXDESC_OFFSET; + ConstructBeacon(adapt, &ReservedPagePacket[BufIndex], &BeaconLength); + + /* When we count the first page size, we need to reserve description size for the RSVD */ + /* packet, it will be filled in front of the packet in TXPKTBUF. */ + PageNeed = (u8)PageNum_128(TxDescLen + BeaconLength); + /* To reserved 2 pages for beacon buffer. 2010.06.24. */ + if (PageNeed == 1) + PageNeed += 1; + PageNum += PageNeed; + haldata->FwRsvdPageStartOffset = PageNum; + + BufIndex += PageNeed*128; + + /* 3 (2) ps-poll *1 page */ + RsvdPageLoc.LocPsPoll = PageNum; + ConstructPSPoll(adapt, &ReservedPagePacket[BufIndex], &PSPollLength); + rtl8188e_fill_fake_txdesc(adapt, &ReservedPagePacket[BufIndex-TxDescLen], PSPollLength, true, false); + + PageNeed = (u8)PageNum_128(TxDescLen + PSPollLength); + PageNum += PageNeed; + + BufIndex += PageNeed*128; + + /* 3 (3) null data * 1 page */ + RsvdPageLoc.LocNullData = PageNum; + ConstructNullFunctionData(adapt, &ReservedPagePacket[BufIndex], &NullDataLength, get_my_bssid(&pmlmeinfo->network), false, 0, 0, false); + rtl8188e_fill_fake_txdesc(adapt, &ReservedPagePacket[BufIndex-TxDescLen], NullDataLength, false, false); + + PageNeed = (u8)PageNum_128(TxDescLen + NullDataLength); + PageNum += PageNeed; + + BufIndex += PageNeed*128; + + /* 3 (4) probe response * 1page */ + RsvdPageLoc.LocProbeRsp = PageNum; + ConstructProbeRsp(adapt, &ReservedPagePacket[BufIndex], &ProbeRspLength, get_my_bssid(&pmlmeinfo->network), false); + rtl8188e_fill_fake_txdesc(adapt, &ReservedPagePacket[BufIndex-TxDescLen], ProbeRspLength, false, false); + + PageNeed = (u8)PageNum_128(TxDescLen + ProbeRspLength); + PageNum += PageNeed; + + BufIndex += PageNeed*128; + + /* 3 (5) Qos null data */ + RsvdPageLoc.LocQosNull = PageNum; + ConstructNullFunctionData(adapt, &ReservedPagePacket[BufIndex], + &QosNullLength, get_my_bssid(&pmlmeinfo->network), true, 0, 0, false); + rtl8188e_fill_fake_txdesc(adapt, &ReservedPagePacket[BufIndex-TxDescLen], QosNullLength, false, false); + + PageNeed = (u8)PageNum_128(TxDescLen + QosNullLength); + PageNum += PageNeed; + + TotalPacketLen = BufIndex + QosNullLength; + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(adapt, pattrib); + pattrib->qsel = 0x10; + pattrib->last_txcmdsz = TotalPacketLen - TXDESC_OFFSET; + pattrib->pktlen = pattrib->last_txcmdsz; + memcpy(pmgntframe->buf_addr, ReservedPagePacket, TotalPacketLen); + + rtw_hal_mgnt_xmit(adapt, pmgntframe); + + DBG_88E("%s: Set RSVD page location to Fw\n", __func__); + FillH2CCmd_88E(adapt, H2C_COM_RSVD_PAGE, sizeof(RsvdPageLoc), (u8 *)&RsvdPageLoc); + +exit: + kfree(ReservedPagePacket); +} + +void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *adapt, u8 mstatus) +{ + struct hal_data_8188e *haldata = GET_HAL_DATA(adapt); + struct mlme_ext_priv *pmlmeext = &(adapt->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + bool bSendBeacon = false; + bool bcn_valid = false; + u8 DLBcnCount = 0; + u32 poll = 0; + +_func_enter_; + + DBG_88E("%s mstatus(%x)\n", __func__, mstatus); + + if (mstatus == 1) { + /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */ + /* Suggested by filen. Added by tynli. */ + rtw_write16(adapt, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid)); + /* Do not set TSF again here or vWiFi beacon DMA INT will not work. */ + + /* Set REG_CR bit 8. DMA beacon by SW. */ + haldata->RegCR_1 |= BIT0; + rtw_write8(adapt, REG_CR+1, haldata->RegCR_1); + + /* Disable Hw protection for a time which revserd for Hw sending beacon. */ + /* Fix download reserved page packet fail that access collision with the protection time. */ + /* 2010.05.11. Added by tynli. */ + rtw_write8(adapt, REG_BCN_CTRL, rtw_read8(adapt, REG_BCN_CTRL)&(~BIT(3))); + rtw_write8(adapt, REG_BCN_CTRL, rtw_read8(adapt, REG_BCN_CTRL)|BIT(4)); + + if (haldata->RegFwHwTxQCtrl&BIT6) { + DBG_88E("HalDownloadRSVDPage(): There is an Adapter is sending beacon.\n"); + bSendBeacon = true; + } + + /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */ + rtw_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl&(~BIT6))); + haldata->RegFwHwTxQCtrl &= (~BIT6); + + /* Clear beacon valid check bit. */ + rtw_hal_set_hwreg(adapt, HW_VAR_BCN_VALID, NULL); + DLBcnCount = 0; + poll = 0; + do { + /* download rsvd page. */ + SetFwRsvdPagePkt(adapt, false); + DLBcnCount++; + do { + rtw_yield_os(); + /* rtw_mdelay_os(10); */ + /* check rsvd page download OK. */ + rtw_hal_get_hwreg(adapt, HW_VAR_BCN_VALID, (u8 *)(&bcn_valid)); + poll++; + } while (!bcn_valid && (poll%10) != 0 && !adapt->bSurpriseRemoved && !adapt->bDriverStopped); + } while (!bcn_valid && DLBcnCount <= 100 && !adapt->bSurpriseRemoved && !adapt->bDriverStopped); + + if (adapt->bSurpriseRemoved || adapt->bDriverStopped) + ; + else if (!bcn_valid) + DBG_88E("%s: 1 Download RSVD page failed! DLBcnCount:%u, poll:%u\n", __func__, DLBcnCount, poll); + else + DBG_88E("%s: 1 Download RSVD success! DLBcnCount:%u, poll:%u\n", __func__, DLBcnCount, poll); + /* */ + /* We just can send the reserved page twice during the time that Tx thread is stopped (e.g. pnpsetpower) */ + /* becuase we need to free the Tx BCN Desc which is used by the first reserved page packet. */ + /* At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return */ + /* the beacon TCB in the following code. 2011.11.23. by tynli. */ + /* */ + + /* Enable Bcn */ + rtw_write8(adapt, REG_BCN_CTRL, rtw_read8(adapt, REG_BCN_CTRL)|BIT(3)); + rtw_write8(adapt, REG_BCN_CTRL, rtw_read8(adapt, REG_BCN_CTRL)&(~BIT(4))); + + /* To make sure that if there exists an adapter which would like to send beacon. */ + /* If exists, the origianl value of 0x422[6] will be 1, we should check this to */ + /* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ + /* the beacon cannot be sent by HW. */ + /* 2010.06.23. Added by tynli. */ + if (bSendBeacon) { + rtw_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl|BIT6)); + haldata->RegFwHwTxQCtrl |= BIT6; + } + + /* Update RSVD page location H2C to Fw. */ + if (bcn_valid) { + rtw_hal_set_hwreg(adapt, HW_VAR_BCN_VALID, NULL); + DBG_88E("Set RSVD page location to Fw.\n"); + } + + /* Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli. */ + /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */ + haldata->RegCR_1 &= (~BIT0); + rtw_write8(adapt, REG_CR+1, haldata->RegCR_1); + } +_func_exit_; +} + +void rtl8188e_set_p2p_ps_offload_cmd(struct adapter *adapt, u8 p2p_ps_state) +{ +#ifdef CONFIG_88EU_P2P + struct hal_data_8188e *haldata = GET_HAL_DATA(adapt); + struct wifidirect_info *pwdinfo = &(adapt->wdinfo); + struct P2P_PS_Offload_t *p2p_ps_offload = &haldata->p2p_ps_offload; + u8 i; + +_func_enter_; + + switch (p2p_ps_state) { + case P2P_PS_DISABLE: + DBG_88E("P2P_PS_DISABLE\n"); + _rtw_memset(p2p_ps_offload, 0, 1); + break; + case P2P_PS_ENABLE: + DBG_88E("P2P_PS_ENABLE\n"); + /* update CTWindow value. */ + if (pwdinfo->ctwindow > 0) { + p2p_ps_offload->CTWindow_En = 1; + rtw_write8(adapt, REG_P2P_CTWIN, pwdinfo->ctwindow); + } + + /* hw only support 2 set of NoA */ + for (i = 0; i < pwdinfo->noa_num; i++) { + /* To control the register setting for which NOA */ + rtw_write8(adapt, REG_NOA_DESC_SEL, (i << 4)); + if (i == 0) + p2p_ps_offload->NoA0_En = 1; + else + p2p_ps_offload->NoA1_En = 1; + + /* config P2P NoA Descriptor Register */ + rtw_write32(adapt, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]); + rtw_write32(adapt, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]); + rtw_write32(adapt, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]); + rtw_write8(adapt, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]); + } + + if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) { + /* rst p2p circuit */ + rtw_write8(adapt, REG_DUAL_TSF_RST, BIT(4)); + + p2p_ps_offload->Offload_En = 1; + + if (pwdinfo->role == P2P_ROLE_GO) { + p2p_ps_offload->role = 1; + p2p_ps_offload->AllStaSleep = 0; + } else { + p2p_ps_offload->role = 0; + } + + p2p_ps_offload->discovery = 0; + } + break; + case P2P_PS_SCAN: + DBG_88E("P2P_PS_SCAN\n"); + p2p_ps_offload->discovery = 1; + break; + case P2P_PS_SCAN_DONE: + DBG_88E("P2P_PS_SCAN_DONE\n"); + p2p_ps_offload->discovery = 0; + pwdinfo->p2p_ps_state = P2P_PS_ENABLE; + break; + default: + break; + } + + FillH2CCmd_88E(adapt, H2C_PS_P2P_OFFLOAD, 1, (u8 *)p2p_ps_offload); +#endif + +_func_exit_; +} diff --git a/drivers/staging/rtl8188eu/hal/rtl8188e_dm.c b/drivers/staging/rtl8188eu/hal/rtl8188e_dm.c new file mode 100644 index 000000000000..9c2e7a20c09e --- /dev/null +++ b/drivers/staging/rtl8188eu/hal/rtl8188e_dm.c @@ -0,0 +1,268 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/* */ +/* Description: */ +/* */ +/* This file is for 92CE/92CU dynamic mechanism only */ +/* */ +/* */ +/* */ +#define _RTL8188E_DM_C_ + +#include +#include + +#include + +static void dm_CheckStatistics(struct adapter *Adapter) +{ +} + +/* Initialize GPIO setting registers */ +static void dm_InitGPIOSetting(struct adapter *Adapter) +{ + u8 tmp1byte; + + tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG); + tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT); + + rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte); +} + +/* */ +/* functions */ +/* */ +static void Init_ODM_ComInfo_88E(struct adapter *Adapter) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter); + struct dm_priv *pdmpriv = &hal_data->dmpriv; + struct odm_dm_struct *dm_odm = &(hal_data->odmpriv); + u8 cut_ver, fab_ver; + + /* Init Value */ + _rtw_memset(dm_odm, 0, sizeof(dm_odm)); + + dm_odm->Adapter = Adapter; + + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_PLATFORM, ODM_CE); + + if (Adapter->interface_type == RTW_GSPI) + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO); + else + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_INTERFACE, Adapter->interface_type);/* RTL871X_HCI_TYPE */ + + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_IC_TYPE, ODM_RTL8188E); + + fab_ver = ODM_TSMC; + cut_ver = ODM_CUT_A; + + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_FAB_VER, fab_ver); + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_CUT_VER, cut_ver); + + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(hal_data->VersionID)); + + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_PATCH_ID, hal_data->CustomerID); + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_BWIFI_TEST, Adapter->registrypriv.wifi_spec); + + + if (hal_data->rf_type == RF_1T1R) + ODM_CmnInfoUpdate(dm_odm, ODM_CMNINFO_RF_TYPE, ODM_1T1R); + else if (hal_data->rf_type == RF_2T2R) + ODM_CmnInfoUpdate(dm_odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R); + else if (hal_data->rf_type == RF_1T2R) + ODM_CmnInfoUpdate(dm_odm, ODM_CMNINFO_RF_TYPE, ODM_1T2R); + + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_RF_ANTENNA_TYPE, hal_data->TRxAntDivType); + + pdmpriv->InitODMFlag = ODM_RF_CALIBRATION | + ODM_RF_TX_PWR_TRACK; + + ODM_CmnInfoUpdate(dm_odm, ODM_CMNINFO_ABILITY, pdmpriv->InitODMFlag); +} + +static void Update_ODM_ComInfo_88E(struct adapter *Adapter) +{ + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv; + struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter); + struct odm_dm_struct *dm_odm = &(hal_data->odmpriv); + struct dm_priv *pdmpriv = &hal_data->dmpriv; + int i; + + pdmpriv->InitODMFlag = ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_PWR_SAVE | + ODM_MAC_EDCA_TURBO | + ODM_RF_CALIBRATION | + ODM_RF_TX_PWR_TRACK; + if (hal_data->AntDivCfg) + pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV; + + if (Adapter->registrypriv.mp_mode == 1) { + pdmpriv->InitODMFlag = ODM_RF_CALIBRATION | + ODM_RF_TX_PWR_TRACK; + } + + ODM_CmnInfoUpdate(dm_odm, ODM_CMNINFO_ABILITY, pdmpriv->InitODMFlag); + + ODM_CmnInfoHook(dm_odm, ODM_CMNINFO_TX_UNI, &(Adapter->xmitpriv.tx_bytes)); + ODM_CmnInfoHook(dm_odm, ODM_CMNINFO_RX_UNI, &(Adapter->recvpriv.rx_bytes)); + ODM_CmnInfoHook(dm_odm, ODM_CMNINFO_WM_MODE, &(pmlmeext->cur_wireless_mode)); + ODM_CmnInfoHook(dm_odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(hal_data->nCur40MhzPrimeSC)); + ODM_CmnInfoHook(dm_odm, ODM_CMNINFO_SEC_MODE, &(Adapter->securitypriv.dot11PrivacyAlgrthm)); + ODM_CmnInfoHook(dm_odm, ODM_CMNINFO_BW, &(hal_data->CurrentChannelBW)); + ODM_CmnInfoHook(dm_odm, ODM_CMNINFO_CHNL, &(hal_data->CurrentChannel)); + ODM_CmnInfoHook(dm_odm, ODM_CMNINFO_NET_CLOSED, &(Adapter->net_closed)); + ODM_CmnInfoHook(dm_odm, ODM_CMNINFO_MP_MODE, &(Adapter->registrypriv.mp_mode)); + ODM_CmnInfoHook(dm_odm, ODM_CMNINFO_SCAN, &(pmlmepriv->bScanInProcess)); + ODM_CmnInfoHook(dm_odm, ODM_CMNINFO_POWER_SAVING, &(pwrctrlpriv->bpower_saving)); + ODM_CmnInfoInit(dm_odm, ODM_CMNINFO_RF_ANTENNA_TYPE, hal_data->TRxAntDivType); + + for (i = 0; i < NUM_STA; i++) + ODM_CmnInfoPtrArrayHook(dm_odm, ODM_CMNINFO_STA_STATUS, i, NULL); +} + +void rtl8188e_InitHalDm(struct adapter *Adapter) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter); + struct dm_priv *pdmpriv = &hal_data->dmpriv; + struct odm_dm_struct *dm_odm = &(hal_data->odmpriv); + + dm_InitGPIOSetting(Adapter); + pdmpriv->DM_Type = DM_Type_ByDriver; + pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE; + Update_ODM_ComInfo_88E(Adapter); + ODM_DMInit(dm_odm); + Adapter->fix_rate = 0xFF; +} + +void rtl8188e_HalDmWatchDog(struct adapter *Adapter) +{ + bool fw_cur_in_ps = false; + bool fw_ps_awake = true; + u8 hw_init_completed = false; + struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter); + + _func_enter_; + hw_init_completed = Adapter->hw_init_completed; + + if (!hw_init_completed) + goto skip_dm; + + fw_cur_in_ps = Adapter->pwrctrlpriv.bFwCurrentInPSMode; + rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&fw_ps_awake)); + + /* Fw is under p2p powersaving mode, driver should stop dynamic mechanism. */ + /* modifed by thomas. 2011.06.11. */ + if (Adapter->wdinfo.p2p_ps_mode) + fw_ps_awake = false; + + if (hw_init_completed && ((!fw_cur_in_ps) && fw_ps_awake)) { + /* Calculate Tx/Rx statistics. */ + dm_CheckStatistics(Adapter); + + _func_exit_; + } + + /* ODM */ + if (hw_init_completed) { + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + u8 bLinked = false; + + if ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE))) { + if (Adapter->stapriv.asoc_sta_count > 2) + bLinked = true; + } else {/* Station mode */ + if (check_fwstate(pmlmepriv, _FW_LINKED)) + bLinked = true; + } + + ODM_CmnInfoUpdate(&hal_data->odmpriv, ODM_CMNINFO_LINK, bLinked); + ODM_DMWatchdog(&hal_data->odmpriv); + } +skip_dm: + /* Check GPIO to determine current RF on/off and Pbc status. */ + /* Check Hardware Radio ON/OFF or not */ + return; +} + +void rtl8188e_init_dm_priv(struct adapter *Adapter) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter); + struct dm_priv *pdmpriv = &hal_data->dmpriv; + struct odm_dm_struct *podmpriv = &hal_data->odmpriv; + + _rtw_memset(pdmpriv, 0, sizeof(struct dm_priv)); + Init_ODM_ComInfo_88E(Adapter); + ODM_InitDebugSetting(podmpriv); +} + +void rtl8188e_deinit_dm_priv(struct adapter *Adapter) +{ +} + +/* Add new function to reset the state of antenna diversity before link. */ +/* Compare RSSI for deciding antenna */ +void AntDivCompare8188E(struct adapter *Adapter, struct wlan_bssid_ex *dst, struct wlan_bssid_ex *src) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter); + + if (0 != hal_data->AntDivCfg) { + /* select optimum_antenna for before linked =>For antenna diversity */ + if (dst->Rssi >= src->Rssi) {/* keep org parameter */ + src->Rssi = dst->Rssi; + src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna; + } + } +} + +/* Add new function to reset the state of antenna diversity before link. */ +u8 AntDivBeforeLink8188E(struct adapter *Adapter) +{ + struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter); + struct odm_dm_struct *dm_odm = &hal_data->odmpriv; + struct sw_ant_switch *dm_swat_tbl = &dm_odm->DM_SWAT_Table; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + + /* Condition that does not need to use antenna diversity. */ + if (hal_data->AntDivCfg == 0) + return false; + + if (check_fwstate(pmlmepriv, _FW_LINKED)) + return false; + + if (dm_swat_tbl->SWAS_NoLink_State == 0) { + /* switch channel */ + dm_swat_tbl->SWAS_NoLink_State = 1; + dm_swat_tbl->CurAntenna = (dm_swat_tbl->CurAntenna == Antenna_A) ? Antenna_B : Antenna_A; + + rtw_antenna_select_cmd(Adapter, dm_swat_tbl->CurAntenna, false); + return true; + } else { + dm_swat_tbl->SWAS_NoLink_State = 0; + return false; + } +}