From: Jesper Nilsson <jesper.nilsson@axis.com>
Date: Tue, 3 Aug 2010 16:01:06 +0000 (+0200)
Subject: CRIS: Update for ARTPEC-3
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=7ec280c52ca5aa1448cd16ae77dd44755413db2b;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git

CRIS: Update for ARTPEC-3

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
---

diff --git a/arch/cris/arch-v32/mm/init.c b/arch/cris/arch-v32/mm/init.c
index caeb921a92ea..0768bc409ca8 100644
--- a/arch/cris/arch-v32/mm/init.c
+++ b/arch/cris/arch-v32/mm/init.c
@@ -27,8 +27,7 @@ extern void tlb_init(void);
  * at kseg_4 thus the ksegs are set up again. Also clear the TLB and do various
  * other paging stuff.
  */
-void __init
-cris_mmu_init(void)
+void __init cris_mmu_init(void)
 {
 	unsigned long mmu_config;
 	unsigned long mmu_kbase_hi;
@@ -55,14 +54,23 @@ cris_mmu_init(void)
 	/* Initialise the TLB. Function found in tlb.c. */
 	tlb_init();
 
-	/* Enable exceptions and initialize the kernel segments. */
+	/*
+	 * Enable exceptions and initialize the kernel segments.
+	 * See head.S for differences between ARTPEC-3 and ETRAX FS.
+	 */
 	mmu_config = ( REG_STATE(mmu, rw_mm_cfg, we, on)        |
 		       REG_STATE(mmu, rw_mm_cfg, acc, on)       |
 		       REG_STATE(mmu, rw_mm_cfg, ex, on)        |
 		       REG_STATE(mmu, rw_mm_cfg, inv, on)       |
+#ifdef CONFIG_CRIS_MACH_ARTPEC3
+		       REG_STATE(mmu, rw_mm_cfg, seg_f, page)   |
+		       REG_STATE(mmu, rw_mm_cfg, seg_e, page)   |
+		       REG_STATE(mmu, rw_mm_cfg, seg_d, linear) |
+#else
 		       REG_STATE(mmu, rw_mm_cfg, seg_f, linear) |
 		       REG_STATE(mmu, rw_mm_cfg, seg_e, linear) |
 		       REG_STATE(mmu, rw_mm_cfg, seg_d, page)   |
+#endif
 		       REG_STATE(mmu, rw_mm_cfg, seg_c, linear) |
 		       REG_STATE(mmu, rw_mm_cfg, seg_b, linear) |
 #ifndef CONFIG_ETRAX_VCS_SIM
@@ -81,9 +89,15 @@ cris_mmu_init(void)
 		       REG_STATE(mmu, rw_mm_cfg, seg_1, page)   |
 		       REG_STATE(mmu, rw_mm_cfg, seg_0, page));
 
+	/* See head.S for differences between ARTPEC-3 and ETRAX FS. */
 	mmu_kbase_hi = ( REG_FIELD(mmu, rw_mm_kbase_hi, base_f, 0x0) |
+#ifdef CONFIG_CRIS_MACH_ARTPEC3
+			 REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x0) |
+			 REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x5) |
+#else
 			 REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x8) |
 			 REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x0) |
+#endif
                          REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x4) |
 			 REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) |
 #ifndef CONFIG_ETRAX_VCS_SIM
@@ -129,8 +143,7 @@ cris_mmu_init(void)
 	SUPP_REG_WR(RW_GC_CFG, 0xf); /* IMMU, DMMU, ICache, DCache on */
 }
 
-void __init
-paging_init(void)
+void __init paging_init(void)
 {
 	int i;
 	unsigned long zones_size[MAX_NR_ZONES];