From: Sylwester Nawrocki Date: Mon, 17 Jul 2017 12:39:21 +0000 (+0200) Subject: clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=7df45a532c5ee3efe106e8a9042a3524b0b587b1;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks This allows clk rate propagation up to the clock tree so EPLL can be reprogrammed indirectly when setting rate of the Audio Subsystem clocks. The advantage is that sound machine driver can operate only on the leaf clocks rather than explicitly re-configuring the root clock (EPLL). Signed-off-by: Sylwester Nawrocki --- diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 1fab56f396d4..b117783ed404 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -180,7 +180,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) } clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), - CLK_SET_RATE_NO_REPARENT, + CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); cdclk = devm_clk_get(&pdev->dev, "cdclk"); @@ -195,11 +195,11 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(NULL, "dout_srp", - "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4, - 0, &lock); + "mout_audss", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, - "dout_aud_bus", "dout_srp", 0, + "dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(NULL, "dout_i2s",